An adiabatic logic is a technique to design low power digital VLSI’s. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2 μm CMOS process. The experimental results show that the multiplier was opera...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

Arithmetic and Logic Unit (ALU), core unit of a processor, when used for scientific computations, will spend more time in multiplications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reducing delay in the multiplier reduces the overall computation time. Wallace multipliers perform in parallel, resulting in high speed. It uses...

Small processors can be especially useful in massively parallel architectures. This paper considers multiprecision division algorithms on an 8-bit processor (the Kestrel processor, currently in fabrication) that includes a small amount of memory and an 8-bit multiplier. We evaluate several variations of the Newton-Raphson reciprocal approximation methods for use with division. Our final singlep...

The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then shows the architecture for a 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra. The paper then extends multiplication to 16×16 Vedic multiplier using "Nikhilam Sutra" technique. The 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra uses four 8×8 Ved...

At Crypto 2009 [1], Bernstein initiated an optimization of Karatsuba formula for binary polynomial multiplication by reorganizing the computations in the reconstruction part of two recursions of the formula. This approach was generalized in [10] to an arbitrary number of recursions resulting in the best known bit parallel multiplier based on Karatsuba formula. In this paper we extend this appro...

A hybrid radix-4/radix-8 architecture targeted for high bit, general purpose, digital multipliers is presented as a compromise between the high speed of a radix-4 multiplier architecture and the low power dissipation of a radix-8 multiplier architecture. In this hybrid radix4/radix-8 multiplier architecture, the performance bottleneck of a radix-8 multiplier, the generation of three times the m...

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signi cantly reduced by a technique known as truncated multiplication. With this technique, the least ...

This paper proposes a novel approach for an optimal multi-objective optimization for VLSI implementation of Artificial Neural Network (ANN) which is area-power-speed efficient and has high degree of accuracy and dynamic range. A VLSI implementation of feed forward neural network in floating point arithmetic IEEE-754 single precision 32 bit format is presented that makes the use of digital weigh...