The design and architecture of a memory test synthesis framework for automatic generation, insertion and veriication of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The exibility and eeciency of the framework are demonstrated by showing that memory BIST units with diierent architecture and characteristics could be...

1 This work was supported by DFG grant WU 245/1-3 Abstract Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The de...

In this paper, we present a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power /energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.

The thesis consists of three sections, developing models of intuitionistic set theory in suitable categories. First, the categorical framework in which models are constructed is reviewed, and the theory of all such models, called Basic Intuitionistic Set Theory (BIST), is stated; second, we give a notion of an ideal over a category, with which one can build a model of BIST in which a given topo...

Analog and Mixed-Signal BIST is alive, well, and here now. It works and it saves time and money. There are people and interests ho would like you to believe otherwise. w Position: It is true that there have been a great number of different research efforts into the area of Analog and Mixed Signal BIST. And most efforts appear to be very insular – they are the efforts of a single entity. Seldom ...

As the density of VLSI circuits increases, it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benefits but also interesting technical opportunities with respect to hierarchical testing and the reuse of test logic during the application of the circuit. Starting with an overview on test problems, test applications an...

Formerly, IC manufacturers applied DFT and BIST to increase yield and the reliability. However, how to balance redundancy utilization in an embedded memory core is still not known. Choi et al. proposed an approach to balance DFT and BIST. In this paper, some technical background is commented.

This paper compares the performance of linear and non-linear machines when they are used as the Pseudo Random Pattern Generators (PRPG) to detect faults in sequential circuits. Both transition test and fault simulation experiments are conducted. Results show that the non-linear machines have higher transition capability and exhibit better performance than the linear machine.

Microprocessor design techniques have evolved to a point where large systems, such as S/390@ servers, can be constructed using relatively few, but very complex, applicationspecific integrated circuits (ASICs). Delivery of a quality design in a timely fashion requires that several design activities progress simultaneously, with different types of verification used within the various design disci...