The design and implementation of a flexible LDPC decoder able to cope with different codes, is gathering an increasing interest in the scientific community. Roughly speaking, a flexible decoder exhibits the remarkable ability of being able to decode different codes resorting to the same hardware. In this paper we present a novel decoder architecture specifically devised to present an high flexi...

This paper is aimed to optimize the binary LDPC decoder which has been shown to outperform commonly used codes for many communications and storage channels. Currently proposed binary LDPC decoder architectures have very high rates close to the channel capacity for the large code word length, in this research work we had presented a decoding algorithm based on belief propagation and provide deta...

Although film matrix surround decoders are primarily four channel devices, with a single channel devoted to sound the sides and the rear, in practice there are almost always two or more surround speakers. These speakers are driven in parallel, with in some cases a delay modulation to “decorrelate” the single surround channel. There is substantial interference between the various loudspeakers, r...

395 Abstract—Reed-Solomon Codes are popularly used for error correction in many applications like storage devices (CD, DVD), wireless communications, high speed modems and satellite communications. In this paper, a modified scheme for programmable generator polynomial based Reed-Solomon encoder and decoder has been proposed. The works reported in this paper corrects errors in derived equations ...

With the increase of information and data types, high-throughput and flexible memory-based VLC decoder is required for userdefined coding tables to achieve higher compression ratio. In this paper, we present a memory-based VLC decoder which is quite suitable for the applications with user-defined tables. By parallel loading data into memories, the coding tables can be changed with much less tim...

In this work, a high performance LDPC decoder architecture is presented. It is a partially-parallel architecture for low-complexity consideration. In order to eliminate the idling time and hardware complexity in conventional partially-parallel decoders, the decoding process, decoder architecture and memory structure are optimized. Particularly, the parity-check matrix is optimally partitioned i...

A versatile Reed-Solomon (RS) decoder structure is developed based on the time-domain decoding algorithm (transform decoding without transforms). In this paper, the algorithm is restructured and a method is given to decode any RS code generated by any generator polynomial. The main advantage of the introduced decoder structure is the versatility. By versatile decoder we mean a decoder that can ...

Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of convolution codes, at the receiver end Viterbi Decoder is being employed. The parameters of Viterbi algorithm can be changed to suit a specific application. The high speed and small area are two important design parameter...

AbstractImplementation of the viterbi decoder in the FPGA plays a dominant role for power and high speed mechanisms. The viterbi decoder is the most efficient decoder. It is commonly used in a wide range of communication and data storage applications. It uses trellis coded modulation (TCM) technique to find the trellis path in the circuit. Here, pre-computation techniques have been adopted for ...