This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM counterparts. This design can be used as cache memory in processors and lowpower portable devices. The proposed SRAM cell features ~13% area reduction compared...

This work describes a 6b 1.4GS/s 65nm CMOS DAC based on a current cell matrix with a 2-D INL bounded switching scheme. The proposed switching scheme reduces current matching errors in both row and column lines with a simple rowcolumn decoder. The proposed area-efficient deglitching circuit minimizes the timing error of each current cell and reduces the required number of transistors by 40% comp...

The growing markets for low-power electronic devices energized by battery have created the need smaller power-efficient chips to prevent frequent charging of source. Nowadays market capitalization appliances is expected grow from USD 4.9 billion 2022 7.9 2027 as per global forecast published markets. main factor leading growth low power electronics includes demand energy saving components, mini...

This paper presents a complementary current-mode 2nd order Gm-C filter for 5G and other broadband applications. The structure is based on 2 differential pairs in to achieve both low noise high frequency performances. A bandwidth of higher than 1GHz achieved with gain 0dB an in-band IIP3 29dBm, consuming less 27mW from 1.8V supply. fabricated 65nm CMOS process core circuit area 0.1mm × 0.08mm.

Efficient Transmitters for Wireless Communications in Nanoscale CMOS Technology by Debopriyo Chowdhury Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California, Berkeley Professor Ali M. Niknejad, Chair The last decade has witnessed a tremendous growth in wireless communications. Todays consumers demand wireless systems that are low-cost, power e...

This paper presents an all-digital second-order ΔΣ time-to-digital converter (TDC) by using switched-ring oscillator (SRO) and gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using the SRO, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the SROs. The prototype TDC achieves 148fsr...

In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. This paper presents a design of input stage of Operational Amplifier i.e cascode differential amplifier using a standard 65nm CMOS Technology.A comparison betweem gate-driven, bulk-driven and cascode bulk driven bulk-driven differential amplifier is described. The Results demonstrate t...

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3– 1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giv...

A fully-digital VCO-based ADC featuring a novel beat frequency detection scheme is demonstrated in 65nm LP CMOS. The proposed beat frequency based ADC is unique compared to previous VCO-based ADCs in that it is highly effective in measuring extremely small changes (e.g., 0.01%) in the VCO frequency within a short sampling time (e.g., 100 VCO periods). Direct amplifier-less A-to-D conversion of ...