This paper will describe aspects relating the modelling of a mixed-signal system with the aim to describe the system in a single language prior to any detailed implementation strategy. With reference to a communications system modelling case study, VHDL-AMS, an extension to the industry standard VHDL Hardware Description Language (HDL) for digital circuits and systems, will be used. Recently, t...

HML (Hardware ML) is an innovative hardware description language based on the functional programming language SML (Standard ML). HML is a high-order language that supports polymorphic functions. HML's advanced type system provides many constructs that are important to hardware descriptions but are lacking in the more mature, widely used hardware description languages such as VHDL and Verilog. I...

The aim of this paper is to present an approach that allows the generation of VHDL from system level speci cations in SDL. Our approach overcome the main known problem encountered by previous work which is the communication between di erent processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that support a powe...

by Mark Dean Mueller With the increasing use of mixed signal analog and digital technologies in circuit design, there becomes a growing need for a method to simulate such circuits quickly, easily and accurately. Modeling the components structurally with an analog simulation tool is a common technique. A more powerful method would be to behaviorally model both types of components at a higher lev...

Dedicated hardware can be used when images and video are acquired and processed. In this paper, a histogram equalization algorithm is written in a Hardware Description Language for future implementation in reconfigurable hardware. The goal of this project is to implement a histogram equalization algorithm using VHDL for a real-time processing system on a Field Programmable Gate Array (FPGA). Th...

Formal tools for the verification of HDL synchronous descriptions are currently in development for both the Verilog [2,3] and VHDL languages [1], but little work has been done on tools able to handle both languages [8]. The well known reason is that VHDL and Verilog's simulation semantics are quite different. So, the task of deciding formally whether two synchronous descriptions written in the ...

A design step transforms a specification into an implementation and may take place on several levels of abstraction. If we want to formally capture the design step in order to reason about its correctness we need on the one hand formal VHDL semantics capturing the static and dynamic aspects of the VHDL simulation model. On the other hand, we need special purpose semantics supporting the use of ...

This paper describes a methodology for top-down design, modeling, and simulation of complete π/4 DQPSK system using hardware description language VHDL-AMS. Two system implementations are considered: with and without Viterbi encoder/decoder. VHDL-AMS implementations of various RF blocks (e.g. a realistic channel model) are developed, the system is simulated, and bit error rate is evaluated in th...

A methodology for modifying VHDL descriptions is the core of this paper. Modifications are performed on general RTL descriptions composed of a mix of control and computation, that is, the typical type of description used for designing at the RT level. Such VHDL descriptions are automatically partitioned into a reference model composed of a controller driving a data-path. We call this transforma...