The popularity of low voltage technologies has grown significantly over the last decade as semiconductor device manufacturers have moved to satisfy market demands for more powerful products, smaller packaging, and longer battery life. By shrinking the size of the features they etch into semiconductor dice, IC manufacturers achieve lower costs, while improving speed and building in more function...

Low-voltage, low-power and medium-accuracy analog-to-digital converters (ADCs) are essential components in portable devices. Low-voltage operation of these ADCs poses three major challenges. First, the floating switches required in conventional switched-capacitor implementations are not operational for very low supply voltages. Second, reduced supply voltage translates to reduced signal power, ...

The NULL Cycle Reduction (NCR) technique can be used to improve the performance of a NULL Convention Logic (NCL) circuit at the expense of power and area. However, by decreasing the supply voltage, the power of the NCR circuit can be reduced. Since NCR has increased performance, it should be possible to reduce supply voltage to decrease overall power while maintaining the original performance o...

High-performance and low-power are the two main criteria in modern digital design. Level converters are important to transfer low voltage input swing signal among the circuits operating at different voltages to get high voltage output swing signal. Previously feedback level converters suffer from short circuit power and long propagation delay. Multi Vth level converters and multiple supply volt...

Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low power clock tree by distributing the clock signal at a lower voltage, and translating it to a higher voltage at the utilization points. Two low power schemes are used: reduced swing and multiple supply voltages. We ana...

Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed and supply voltage ; b) transition activity in presence of noise; c) dynamic energy dissipation; and d) total (dynamic and static) ...

Aggressive voltage scaling to 1 V and below through technology, circuit, and architecture optimization is the key to low-power design. Threshold voltage scaling enables aggressive supply scaling but increases leakage power. Technology and circuit trends to control idle leakage power are presented including MTCMOS, variable VT bulk-CMOS, and variable VT Sol . Power can also be reduced by adaptiv...

Analog switches, which are known to be the bottle-neck for reducing the supply voltage, are analyzed. MOSFET transistors with channel lengths shorter than the minimum feature size (L 0 ) in a given technology are proposed for use as switches operated at a low supply voltage. These MOSFETs have lower threshold voltage and higher punchthrough currents compared to a transistor of L 0 length (due t...

Energy efficiency is a primary concern for microprocessor designers. One very effective approach to improving the energy efficiency is to lower chip supply voltage very near to the transistor threshold voltage. This reduces power consumption dramatically, improving energy efficiency by an order of magnitude. Low voltage operation, however, increases the effects of parameter variation resulting ...

In order to cope with the increasing leakage power and the increasing device variability in VLSI’s, the required control size of both the space-domain and the time-domain is decreasing. This paper shows the several recent fine-grain voltage engineerings for the low power VLSI circuit design. The space-domain fine-grain voltage engineering includes the fine-grain power supply voltage with 3D-str...