When uniprocessors were the norm, Instruction Level Parallelism (ILP) and Data Level Parallelism (DLP) were widely exploited to increase the number of instructions executed per cycle. The main hardware designs that were used to exploit ILP were superscalar and Very Long Instruction Word (VLIW) processors. The VLIW approach implies statically figuring out dependencies between instructions and sc...

The X4CP32 is an architecture that combines both Parallel and reconfigurable paradigms. It consists of grid of Reconfigurable and Programming Unit (RPU), responsible for all the processing and program flow. This paper presents architectural modification in order to maximize the computational use of the Cells in a RPU. A change to a very large instruction word (VLIW) philosophy in the RPU was im...

Technology has seen the development of processor industry right from micro to the latest Nanotechnology with speed being important criteria. Not much attention has been given to the power required to drive these Integrated Circuits. With gaining popularity in mobile computing, developing mobile processors have gained popularity since these processors possess unique properties like low power con...

Rao, Vikram. IA-64 code generation. (Under the direction of Dr. Tom Conte). This work presents an approach to code generation for a new 64-bit Explicitly Parallel Instruction Computing (EPIC) architecture from Intel, called IA-64. The major contribution of this work is the design of a machine independent optimizer, munger, that transforms code generated originally for a Very Long Instruction Wo...

Vikram Rao. IA-64 code generation. (Under the direction of Dr. Tom Conte). This work presents an approach to code generation for a new 64-bit Explicitly Parallel Instruction Computing (EPIC) architecture from Intel, called IA-64. The major contribution of this work is the design of a machine independent optimizer, munger, that transforms code generated originally for a Very Long Instruction Wor...

Typical data-intensive embedded applications have large amounts of instruction-level parallelism that is often exploited with wide-issue VLIW processors. In contrast, event-driven embedded applications are believed to have very little instruction-level parallelism, so these applications often utilize much simpler processor cores. Programmable network interface cards, for example, utilize thread...

This paper presents a novel compiler backend which generates assembly code for Synchronous Transfer Architecture (STA). STA is a Very Long Instruction Word (VLIW) architecture and in addition it uses a non-orthogonal Instruction Set Architecture (ISA). Generating efficient code for this architecture needs highly optimizing techniques. The compiler backend presented in this paper is based on Int...

As modern areas of application for coarse-grained reconfigurable systems digital signal processing, multimedia in embedded devices, and wireless communication can be mentioned among others. These fields include different algorithms with varying complexity and speed requirements. In this paper a new highly parameterizable coarse-grained reconfigurable architecture called weakly programmable proc...

HP and Intel have recently introduced a new style of instruction set architecture called EPIC (Explicitly Parallel Instruction Computing), and a specific architecture called the IPF (Itanium Processor Family). This paper seeks to illustrate the differences between EPIC architectures and former styles of instruction set architectures such as superscalar and VLIW. Several aspects of EPIC architec...

The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU) for a higher instruction issuing rate – the dramatically growing complexity in the register file (RF), and the poor code density. In th...