This paper presents the application of geometric programming for combined high-level and low-level architecture parameter exploration. This paper builds an geometric programming framework for reconfigurable architectures, and presents a full delay and area model of an FPGA. This optimization allows high-level architectural parameter selection and the transistor sizing to be done concurrently. T...

A multi-band CMOS LC Quadrature Voltage Control Oscillator (QVCO) with minimum power consumption is developed to meet the phase noise and frequency band requirements of RFID, Zigbee and Bluetooth standards. To accomplish the multi-band receiving architecture at low power consumption, current switching technique with optimized cross-coupled transistor sizes has been used. A comprehensive analysi...

The temperature dependence of magneto current in the spin spin valve transistor system is theoretically explored based on phenomenological model. We find that the collector current strongly depends on the relative orientation of magnetic moment of ferromagnetic metals due to spin mixing effect. For example, the collector current is decreasing in the parallel case with increasing temperature, an...

The drive performance of a new MOSFET structure, the peak device, resulting from recent doping profile optimizations of a 0.25 mm nMOSFET for 1.5 V supply voltage, is investigated. Explanations for the improved performance are given using two-dimensional device simulation. With an analytical transistor model fitted to the two-dimensional device characteristics, the relevant physical effects are...

In this paper, we propose an analytical approach for the small-signal response of nanometric InGaAs diode which is extracted to the transistor model in ref [1] when the gate is taking away. The exploitation of the small-signal equivalent circuit elements such as the admittance parameters can give significant information about the noise level of the devices by using the Nyquist relation. The ana...

Widely used approaches to modeling random effects and extracting random parameters in matching-critical circuits are based upon models derived under the widely accepted premise that distributed parameter devices can be modeled with lumped parameter models. In this paper, a new stochastic approach based upon a distributed parameter model is presented that offers improvement in predicting the eff...

Rapid energy-delay exploration methodology based on circuit sizing as applied to clocked storage elements is presented. Circuit delay and energy are modeled using improved RC delay model of a transistor. The accuracy of the model is increased by using Logical Effort setup accounting for input signal slope and extraction of technology dependent parameters. The minimal energy-delay curve is gener...

This article focuses on the properties of a fine grained reconfigurable transistor array currently under test at the Jet Propulsion Laboratory (JPL). This Field Programmable Transistor Array (FPTA), is integrated on a Complementary Metal-Oxide Semiconductor (CMOS) chip. The FPTA displrrys advantageous features for hardware evolutionary experiments when comparing to programmable circuits with a ...

The continuous scaling down of feature size in Silicon technology has resulted in several technological and fundamental hindrances. The researchers started to look for new nanoscale devices those can replace CMOS transistors in digital circuits. The nanowire transistor, FinFET, Carbon Nanotube field effect transistor (CNFET), tunnel field effect transistor (TFET), and single electron transistor...

Molecules are attractive to develop nano-electronic devices. In this paper a new type of transistor is realized by using self-organized films of the Guanosine molecule, a modified DNA base. With its 40 nm channel length the transistor is a good starting point for a new class of nano-electronics devices. Experimental current-voltage characteristics are shown. A circuital model is also proposed. ...