A lot of consideration has been given to problems arising due to power dissipation. Different ideas have been proposed by many researchers from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between the power, delay and area. This is why; the designers are required to choose appropriate techniques that satisfy application and product...

In this paper we present Boolean techniques for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates and dynamic PLA implementations. We modify Espresso algorithm by adding our heuristics that bias the logic minimization toward lowering the power dissipation. In o...

The scaling of nanometer technology has had a major impact on the power dissipation of CMOS circuits. As transistor size decreases it has become apparent that leakage power is becoming a dominant fighting force against future technology. In this paper the importance of static power consumption on the design of new and advanced CMOS technology is explored with the investigation of leakage power ...

Level shifter is an interfacing circuit which can interface low core voltage to high input-output voltage. It allows communication between different modules without adding up any extra supply pin. The main objective of the work is to minimize power dissipation in shifter circuit, which is due to different supply voltages in the circuit. The proposed method uses MTCMOS technique, which is one of...

This paper mainly presents Mixed Gate Diffusion Input Full Adder based on static CMOS inverter topology. In this proposed mixed Full Adder topology, GDI Full adders are followed by inverters in the long Full Adder chain to improve the performances as compared to conventional single topology Full adder chain. For any circuits reducing the speed and power dissipation are the important constraints...

Power dissipation in high performance systems requires more expensive packaging. In this situation, low power VLSI design has assumed great importance as an active and rapidly developing field. As the density and operating speed of CMOS VLSI chip increases, power dissipation becomes more significant due to the leakage current when transistor is OFF. This can be observed in both combinational an...

This paper describes a CMOS analogy voltage supper buffer designed to have extremely low static current Consumption as well as high current drive capability. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation. The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the redu...

This study presents the design of low power 9T SRAM cell using dynamic domino logic to achieve low power dissipation. The internal structure of the proposed 9T SRAM has cross coupled dynamic inverters which periodically updates the internal node voltage levels which, increase the read and write stability of the circuit. The SRAM design also has charge keeper transistor which resolves the proble...

Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Lesser be the losses more energy efficient would be the circuit. In this paper, a new approach i.e., Complementary Energy Path Adiabatic Logic (CEPAL), is presented to minimize power dissipation in quasi static energy recovery logic (QSERL). It o...

Keywords: Low-power Adiabatic logic Energy recovery Multiplier a b s t r a c t As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity ...