This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the c...

To reduce the dynamic power consumption in SRAM a new design technique is proposed here. The proposed technique is compared with 8T SRAM cell design technique using 0.18 micron technology. Simulation results indicates that the proposed technique provides an improvement of 64% in bitline leakage ,22.64% in write ‘0’ power, 30.68% in write ‘1’ power over 8T SRAM cell design technique.

A physical unclonable function (PUF), analogous to a human fingerprint, has gained an enormous amount of attention from both academia and industry. SRAM PUF is among one of the popular silicon PUF constructions that exploits random initial power-up states from SRAM cells to extract hardware intrinsic secrets for identification and key generation applications. The advantage of SRAM PUFs is that ...

In energy-aware design, especially for systems with uncertain power sources, asynchronous computation loads which can function under variable power supply have many potential advantages. Fully safe asynchronous loads based on delay insensitivity (DI), however, tend to suffer power and size penalties. As a compromise, delay bundling has been widely used in asynchronous computation, but tradition...

The Present day workstations, low-power processors, computers and super computers are using fast Static Random Access Memory (SRAMs) and will require, in the future, larger density memories with faster access time and minimum power consumption. Acknowledging the intense requirements for power, in current high performance memories of computing devices, the circuit designers have developed a numb...

Technology scaling has enabled us to integrate both memory and logic circuits on a single chip. However, the performance of embedded memory and especially SRAM (Static Random Access Memory) that is widely used in the industry as on the on-chip memory cache in ultra low voltage applications can adversely affect the speed and power efficiency of the overall system. This report discusses the desig...

This paper presents how power is reduced using voltage scaling method. By scaling the voltage down the power will be reduced but the low voltage increases the parametric failures like access, disturb and write. In this paper propose SRAM cell architecture with the application of low voltage for Lower ordered bits & nominal voltage for Higher ordered bits, because for multimedia applications lik...

As CMOS technology down sized into double digit nanometer ranges, variations are a serious concern due to uncertainty in devices and interconnect characteristics. The single event upset (SEU) is changing the state of a memory cell due to the strike of an energetic particle. The single event multiple effects are likely to increase in nanometer CMOS technology due to reduced device size and scali...

Several recent publications have shown that memory errors are common in high-performance computing systems, due to hardware faults in the memory subsystem. With exascale-class systems predicted to have 100-350x more DRAM and SRAM than current systems, these faults are predicted to become more common. Therefore, further study of the faults experienced by DRAM and SRAM is warranted. In this paper...