A new methodology has been developed to measure the mechanical integrity of a bilayer lipid membrane (BLM) formed over porous substrates. A custom test fixture was fabricated in which a stepper motor linear actuator drives a piston in order to apply pressure to a BLM in very fine increments. The pressure, monitored with a pressure transducer, is observed to increase until the BLM reaches its fa...

Many embedded applications can benefit from the flexible custom computing opportunities that FPGA technology offers. The Run-Time Reconfiguration (RTR) of the FPGA as an application is being served provides further flexibility. It gives the opportunity to reuse FPGA space used by custom computing circuits that are not operational in a given time frame. Custom computing circuits can meet very ti...

This paper details the implementation of a highly pipelined 2.5 Gbps Point-to-Point-Protocol Packet Processor (P) aimed for the latest System-on-a-Programmable-Chip (SoPC) technology. Throughput rates beyond 2.5 Gbps based on FPGA technology could be achieved by designing a new highly pipelined and parallel processing architecture for frames and datagrams. A novel pipelined data sorting mechani...

This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a coprocessor to reduce it by more than an order of magnitude. The coprocessor is based on an innovative algorithm known as the MZ-coder and maintains the original coding efficiency with a multiplication-free, non-stalling, fully pipelined architecture with modest hardware ...

In March 2011, a 47-year-old Chinese woman who enjoyed good past health presented to a local general out-patient clinic in Hong Kong with a 2-week history of a mildly painful cord-like structure stretching from the inferior part of the left breast to the umbilicus level (Fig). She had worked as a dishwasher 3 months prior to the appearance of the lesion, a job that required her to carry stacks ...

Using software code to achieve video coding, reduce the cost and increase portability, present a scheme using Altera SOPC to control data coding for MPEG-4 video software compressing system. According to use the DE2 board of Altera, implementing coding image data’s input and output through the USB port on the board, achieves the input image MPEG-4 encoding using the configural NiosII embedded s...

Introduction Reducing power consumption in embedded products that use FPGAs is increasingly important, particularly for battery-powered applications or to reduce heat or cost. You can use parallel algorithms to exploit the parallel architecture of FPGA devices to accomplish more work per clock cycle, allowing you to lower the clock frequency. High-level development tools such as SOPC Builder an...