Thomas Kailath Inform. Systems Lab. Stanford University Stanford, Calif. 94305 A rigorous analysis on the finite precision computational <)Spects of neural network as a pattern classifier via a probabilistic approach is presented. Even though there exist negative results on the capability of perceptron, we show the following positive results: Given n pattern vectors each represented by en bits ...

This paper provides an eficient method t o find all feasible offsets f o r a given separation in a VLSI channel routing problem in one layer. The prior literature considers this task only f o r problenis with no single-sided nets. When single-sided nets are included, the worst-case solution time increases from Q(n) to C2(ii2), where 11 is the number of nets. But we show that if the number of co...

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement and power reduction. Based o...

Many authors have pointed out the need to firm up the ‘fuzzy’ ecosystem management paradigm and develop operationally practical processes to allow forest managers to accommodate more effectively the continuing rapid change in societal perspectives and goals. There are three spatial scales where clear, precise, practical ecosystem management processes are needed: the regional assessment scale, t...

In this paper, we propose an implicit high-order compact (HOC) finite-difference scheme for solving the two-dimensional (2D) unsteady Navier–Stokes (N–S) equations on irregular geometries on orthogonal grids. Our scheme is second order accurate in time and fourth order accurate in space. It is used to solve three pertinent fluid flow problems, namely, the flow decayed by viscosity, the lid-driv...

Introduction Introduction Background Background – – Dynamic power dissipation Dynamic power dissipation – – Glitch reduction Glitch reduction – – Previous LP model Previous LP model Process Process-variation variation-resistant LP model resistant LP model – – Process variation Process variation – – Delay model Delay model – – LP model based on worst LP model based on worst-case timing case timi...

Housing mobility programs enable families living in high-poverty neighborhoods to relocate to lowerpoverty neighborhoods using tenant-based subsidies. Recent research indicates that these programs improve participant outcomes on a number of economic and social outcomes. Can such programs be run at a scale sufficient to help a large proportion of eligible families? Would doing so change the char...

1. The Concept: What is Typical-case Design? This abstract presents my incremental study of the paper previously published at ISQED 2007 [1]. It is expected that I will graduate in March, 2008, under the advice from Toshinori Sato at Kyushu University. The aim of my study is developing a design methodology for the advanced semiconductor technologies, where transistors are unreliable and thus pa...

Bounding the load capacitance at gate outputs is a standard element in today’s electrical correctness methodologies for high-speed digital VLSI design. Bounds on load caps improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise [6]. For clock and test distribution, an additional design requirement is bounding the buffer ...

In this paper we introduce a VLSI priority encoder that uses a novel priority lookahead scheme to reduce the delay for the worse case operation of the circuit, while maintaining a very low transistor count. The encoder's topmost input request has the highest priority; this priority descends linearly. Two design approaches for the priority encoder are presented, one without a priority lookahead ...