We introduce the notion ofstrongly $alpha$-reversible rings which is a strong version of$alpha$-reversible rings, and investigate its properties. We firstgive an example to show that strongly reversible rings need not bestrongly $alpha$-reversible. We next argue about the strong$alpha$-reversibility of some kinds of extensions. A number ofproperties of this version are established. It is shown ...

This paper presents a high speed binary floating point multiplier based on Hybrid Method. To improve speed multiplication of mantissa is done using Hybrid method replacing existing multipliers like Carry Save Multiplier, Dadda Multiplier and Modified Booth Multiplier. Hybrid method is a combination of Dadda Multiplier and Modified Radix-8 Booth Multiplier. The design achieves high speed with ma...

In this paper we proposed a three stage pipelined finite-impulse response (FIR) filter, this FIR filter contains multipliers such as Hybrid multiplier, Booth multiplier algorithm and Array multiplier. In general, multiplication process consists of two parts as multiplicand and multiplier. According to the array multiplier, the numbers of partial products (PP) are equal to the number of bits in ...

Multipliers of reproducing kernel Hilbert spaces can be characterized in terms positivity $n \times n$ matrices analogous to the classical Pick matrix. We study for which it suffices consider bounded size $n$. connect this problem notion subhomogeneity non-selfadjoint operator algebras. Our main results show that multiplier algebras many analytic functions, such as Dirichlet space and Drury-Arv...

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed.  This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...

A 4x4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4x4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus...

A 4x4 and 8x8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4x4 and 8x8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multipli...

Two’s complement multipliers are important for a wide range of applications. Paper describes a technique to reduce by one row the maximum height of the partial product array generated by Radix-4 Booth’s multiplier, without any increase in the delay of the partial product generation stage. The design of 8 bit and 16 bit multiplication scheme using different types of multiplier like Array multipl...

Multiplier is one of the essential element for all digital systems such as digital signal processors, microprocessors etc. In this paper, a new high speed multiplier using booth recoding technique is presented. This algorithm can be implemented by using the radix-8 booth recoding process. The proposed multiplier reduces the partial product array by almost 3/4 th the size of the bits. This reduc...