We discuss the applications of modular self-reconfigurable robots to navigation. We show that greedy algorithms are complete for motion planning over a class of modular reconfigurable robots. We illustrate the application of this result on two self-reconfigurable robot systems we designed and built in our lab: the robotic molecule and the atom. We describe the modules and our locomotion experim...

In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on coarse-grain reconfigurable hardware. The reconfigurable hardware blocks are embedded in a heterogeneous reconfigurable system architecture. The fine-grain part is implemen...

This thesis investigates the feasibility of using reconfigurable computers for scientific applications. We review recent developments in reconfigurable high performance computing. We then present designs and implementation details of various scientific applications that we developed for the SRC-6 reconfigurable computer. We present performance measurements and analysis of the results obtained. ...

ÐThis paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfig...

Reconfigurable computing has become a hot topic in research due to its high-performance and flexibility. In this paper we present a simulator called JRSim for mesh-based reconfigurable architectures. The purpose of this simulator is to provide a platform to evaluate new architectures, and to assist in analysis of algorithms as well as the visualization of their behavior. JRSim is a platform-ind...

A compact reconfigurable antenna integrated with stepped impedance stub (SIS) loaded stepped impedance resonator (SIR) and SIS loaded hexagon stepped impedance resonator (HSIR) for ultra wideband (UWB) applications is proposed in this paper. The reconfigurable UWB antenna can work as a UWB antenna and a dual notch band UWB antenna by controlling the switches ON and OFF. The proposed two notch b...

A new FPGA architecture (reconfigurable datapath architecture, rDPA) for word-oriented datapaths is presented, which has been developed to support a variety of Xputer architectures. In contrast to von Neumann machines an Xputer architecture strongly supports the concept of the “soft ALU” (reconfigurable ALU). Fine grained parallelism is achieved by using simple reconfigurable processing element...

Fixed-point simulation results are used for the performance measure of inverting matrices using a reconfigurable processing element. Matrices are inverted using the Cholesky decomposition algorithm. The reconfigurable processing element is capable of all required mathematical operations. The fixed-point word length analysis is based on simulations of different condition numbers and different ma...