A high-speed and reduced-area lifting architecture for 2D Discrete Wavelet Transform computation and the 2-D DWT Image Decomposition is proposed in this work. Lift scheme is one of the wavelet computation techniques. Prior DWT architectures are mostly constructed on the basic lifting scheme or the flipping structure. In order to attain a critical path with only one multiplier, at least four pip...

This paper presents a novel high-speed, lowcomplexity 128/64-point radix-24 FFT/IFFT processor for the applications in a high-throughput MIMO-OFDM systems. The high radix radix-24 multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. The proposed processor not only supports the operation of FFT/...

Field programmable gate arrays are ideally suited for the implementation of DCT based digital image compression. However, there are several issues that need to be solved. The Multiply-Accumulate Unit (MAC) is the main computational kernel in DIP architectures. The MAC unit establishes the power and the speed of the overall system; it always lies in the critical path. To develop high speed and l...

0740-7475/98/$10.00 © 1998 IEEE 105 MODULE GENERATORS PROVIDED by library vendors supply chip designers with optimized Booth multipliers, which are widely used as embedded cores in both generalpurpose data path structures and specialized digital signal processors. Designers frequently use Booth multipliers in areaand speedcritical parts of complex ICs. Compared to standard array multipliers, Bo...

A rapid and proficient in power requirement multiplier is always vital in electronics industry like DSP, image processing and ALU in microprocessors. Multiplier is such an imperative block w ith respect to power consumption and area occupied in the system. In order to meet the demand for high speed, various parallel array multiplication algorithms have been proposed by a number of authors. The ...

In recent times, DSP algorithms have received increased attention due to rapid advancements in multimedia computing and high-speed wired and wireless communications. In response to these advances, the search for novel implementations of arithmetic-intensive circuitry has intensified. For the portability requirement in telecommunication systems, there is a need for low power hardware implementat...

A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. A novel simple address mapping scheme and the modified radix 4 FFT also proposed. FPGA was majorly used to develop the ASIC IC’s to which ...

In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. But using SPST(Spurious Power Suppression Technique) we can reduce power and the overall performance was elevated. The proposed SPST based radix-4 modified Boo...

The multiplier forms the core of systems such as FIR filters, Digital Signal Processors and Microprocessors etc. This paper presents a model of two different 16X16 bit multipliers. First is Radix-4 Multiplier with SQRT CSLA and Second one is Radix -4 multiplier with Modified SQRT CSLA. Modified Booth Algorithm is used for Partial Products Generation. Wallace Tree Structure is used to accumulate...