A single electron memory was demonstrated in crystalline silicon that has a transistor channel width of ;10 nm and a nanoscale floating gate of dimension ;~7 nm 3 7 nm 3 2 nm!, patterned by electron beam lithography, lift-off, and reactive ion etching. Quantized shift in the threshold voltage and self-limited charging process have been observed at room temperature. Analysis has shown that these...

Paul Hasler and Paul D. Smith Georgia Institute of Technology Atlanta, GA 30332-0250 [email protected] ABSTRACT Recently, we have characterized and modeled oating-gate circuits that adapt their oating-gate charge based upon statistics of the incoming signal. In this paper, we show signal-dependant adaptation in three oating-gate circuits. First, we show classic autozeroing oating-gate ampli...

Rearranging of the logic equations which define the carry lookahead principle and using floating gate circuits allow us to obtain adders with a better performance than the traditional ones. The functions defining functionality of the adder are expressed as threshold functions which have been implemented by resorting to νMOS circuits. A 64 bit adder has been implemented using this approach in a ...

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS tec...

Floating-Gate Memory In article number 2105472, Young-Jun Yu and co-workers systematically design demonstrate multiple bits on non-volatile memory based vdW heterostructure floating-gate (FGM) by tuning the dimensions of 2D materials. A fingerprint mechanism is established that links bit crystals heterostructures. This approach could enable precise generation desired in layered-material-based F...

Conventional Flash memory devices face a scaling issue that will impede memory scaling beyond the 50nm node: a reliability issue involving the tunneling oxide thickness and charge retention. A possible solution is to replace the continuous floating gate, where charge is stored, with a segmented charge storage film, so that leakage through defects in the tunneling oxide would be localized. We fi...

OVERVIEW This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems. Various computational methodologies are used simultaneously to solve problems by mapping pieces of them to the appropriate type of computer. There exists no systematic approach to simultaneously apply analog, dig...

Simple ultra low-voltage floating-gate current scaling and level shifting circuits are presented. The current scaling and level shifting are accomplished using only minimum transistors and floating capacitors. The circuits are extremely small compared to a standard approach to current scaling. Measured results are provided.