The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterog...

This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (...

capacity field-programmable devices have enjoyed a rapidly expanding market and have become widely accepted for the implementation of small to moderately large digital circuits. The two main types of FPDs, field-programmable gate arrays and complex programmable logic devices, are both widely used, each offering particular strengths. FPGAs programmed with static RAM technology are usually based ...

We propose a new general-purpose computer architecture based on programmable logic. It consists of a dual-structured array of cells accommodating a fixed “built-in part” and a freely programmable “plastic part”. We call this composition the “Plastic Cell Architecture” (PCA). The built-in part with its fully connective two-dimensional mesh structure serves as a communication platform based on th...

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how suc...

As transistor feature sizes scale below 100nm, the costs of standard-cell-based application specific integrated circuits (ASICs) are increasing so rapidly that fewer products have sufficient volume to justify the high non-recurring engineering (NRE) costs. Consequently, more designs are relying on fully programmable devices such as field programmable gate arrays (FPGAs). Unfortunately, such ful...

This paper presents an introduction to digital hardware design using Field Programmable Gate Arrays (FPGAs). After a historical introduction and a quick overview of digital design, the internal structure of a generic FPGA is discussed. We then describe the design flow, i.e., the steps needed to go from design idea to actual working hardware. Digital signal processing is an important area where ...

This paper describes the design and implementation of a fully pipelined 64-point Fast Fourier Transform (FFT) in programmable logic. The FFT takes 20-bit fixed point complex numbers as input and after a known pipeline latency produces 20-bit complex values representing the FFT of the input. It is designed to allow continuous input of samples and is therefore suitable for use in real-time system...

This article presents the implementation of a selfreplication algorithm in a Field Programmable Gate Array (FPGA). Whereas previous research on self-replication has been mostly limited to theoretical examples and small problem sizes, this work shows how the Tom Thumb self-replication algorithm can be extended to take into account realistic FPGA architectures and representative processor-scale d...