Experiments to determine the potential for program-level and/or phase-level adaptation of branch predictor configuration for the purpose of total processor energy savings were performed. The performance and energyefficiency of an 8-wide issue, out-of-order processor with six different branch predictors were evaluated on the SPECcpu2000 benchmark suite. Each branch predictor was compared to the ...

This paper indicates a potential security threat which may do harm to distributed computing security. As the program is distributed to run in the remote nodes, adversary may use simulator to produce false results to do tampering. Some sophisticated simulator can give powerful tampering ability to adversary, with the reason explained in this paper. In order to solve this security problem, Real P...

We have been pursuing a research program aimed at enhancing productivity and performance in parallel computing at the Parallel Programming Laboratory of University of Illinois for the past decade. We summarize the basic approach, and why it has improved (and will further improve) both productivity and performance. The centerpiece of our approach is a technique called processor virtualization: t...

We present an architecture called the CAPP (Computing And Prefetching Processor). The CAPP provides high performance for loop-based scientific and signal processing programs by improving memory system performance by providing a decoupled prefetch processor. The prefetch processor improves performance by relieving the main processor of prefetching instruction overhead and allowing the prefetch d...

and have found that it is complete and satisfactory in all respects, and that any and all revisions required by the final examining committee have been made ABSTRACT Scientific and other data-intensive applications often generate memory referencing patterns that exhibit little data reuse, resulting in poor cache utilization and run-times that can be dominated by memory delays. Data prefetching ...

Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor implemented in today’s technology can achieve an increase of 10–60% (geometric mean of 31%) in program speed compared to today’s processors. The processor operates at clock speeds comparable to today’s processors, but ...

1.0 Introduction Typically, the design of complex systems depends very much on the application domain. For example, performance is the most critical design parameter for applications like real-time video compression, whereas validation of the design is the most important point in avionics, and automotive electronics is mainly concerned with the final costs of the product. Hence it is unlikely t...

The PSL-to-Verilog (P2V) compiler can translate a set of assertions about a block-structured software program into a hardware design to be executed concurrently with the execution of the software program. The assertions validate the correctness of the software program without altering its temporal behavior in any way, a result that has never been previously achieved by any online model-checking...

A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor’s on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The pro...