In any integrated circuit power consumption plays a paramount role and is considered as one of the top challenges in International technology roadmap for semiconductors. In this paper, a low power circuit designed to operate in subthreshold region is proposed. Voltage scaling technique is incorporated to reduce dynamic power consumption while static or leakage power is greatly reduced with forc...

Conditional capture and conditional precharge techniques for high-performance flip-flops are reviewed in terms of power and delay. It is found that application of conditional techniques can improve Energy-Delay Product for up to 14% for 50% input activity and save more than 50% in power consumption for quiet input. This property makes conditional methods suitable for high-performance VLSI systems.

A new side-contacted field effect diode (S-FED) structure has beenintroduced as a modified S-FED, which is composed of a diode and planar double gateMOSFET. In this paper, drain current of modified and conventional S-FEDs wereinvestigated in on-state and off-state. For the conventional S-FED, the potential barrierheight between the source and the channel is observed to b...

This paper describes a new design of low power 3-2 compressor circuit for high speed multipliers. Power consumption of proposed 3-2 compressor circuit varies from 0.355 nW to 1.6964 nW and delay varies from 2.0390 ns to 2.0224 ns. Further, power delay product of proposed circuit varies from 7.23×10 -18 (J) to 34.30×10 -18 (J) with varying supply voltage from 1.8V to 3.3V. The proposed compresso...

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS...

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are...

In this paper, we present a performance comparison of existing clocked dynamic comparators. As delay is directly correlated with the submicron scaling, we investigate the performance of the above comparators in terms of delay and Power-Delay Product (PDP). PDP gives the average energy dissipated by the comparator for a single comparison. Simulation results using Mentor Graphics revealed better ...

Length of interconnect and number of repeaters are increasing with the advancement in VLSI Technology. Requirement of repeaters is increasing as the length of interconnect is increasing. The power delay product and frequency of operation plays significant role in designing of repeater. Performance of earlier conventional repeater with the proposed sub-threshold grounded body (STGB) bias repeate...

ABSTRACT : A circuit design for a low-power full adder array-based multiplier in domino logic is proposed. It is based on Wallace tree technique. Clocked architecture results in lower power dissipation and improvements in power-delay product. The proposed technique is general and can be used in all domino logic circuit designs. Higher order multipliers like 16x16, 32x32 may also be implemented ...

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on different digital building blocks are provided to validate the main concepts presented in this paper. Implemented in conventional 0.18μm CMOS ...