In this paper, we explore novel schemes for reducing power consumption in modern enterprise level routers and evaluate their effectiveness in terms of energy saved and impact on router performance. The largest consumers of power within routers are memory, the two biggest culprits being TCAMs and SRAM buffers. Our hardware mechanisms target the TCAM as a potential location to reduce power consum...

In future high-speed self-routing photonic networks based on all-optical time division multiplexing (OTDM) it is highly desirable to carry out packet switching, clock recovery and demultplexing in the optical domain in order to avoid the bottleneck due to the optoelectronics conversion. In this paper we propose a self-routing OTDM node structure composed of an all-optical router and demultiplex...

The Network-on-Chip (NoC) approach for designing (System-on-Chip) SoCs is currently used for overcoming the scalability and efficiency problems of traditional on-chip interconnection schemes, such as shared buses and point-to-point links. NoC design draws on concepts from computer networks to interconnect Intellectual Property (IP) cores in a structured and scalable way, promoting design re-use...

In this paper, we proposed an all optical 4-to-2 encoder that has 4 input and 3 output ports. This device generates a 2 bit binary code based on which input port is active. We used nonlinear photonic crystal ring resonators along with optical power splitter for realizing the proposed encoder. In this device the switching rate and area are obtained about 333 GHz and 612µm2 respectively.

We demonstrate 10 Gbps error free operation through multiple ports of an InP monolithic tunable optical router consisting of eight input wavelength converters and an 8x8 passive arrayed-waveguide grating router.

outers knit together the constituent networks of the global Internet, creating the illusion of a unified whole. While their primary role is to transfer packets from a set of input links to a set of output links, they must also deal with heterogeneous link technologies, provide scheduling support for differential service, and participate in complex distributed algorithms to generate globally coh...

Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. One reason for the low speed is the way that asynchronous routers use to build wide channels. To meet the bandwidth requirement, current routers broaden their channels by synchronizing multiple sub-channels. The C-element tree in the completion detection cir...

Modern networks require the flexibility to support new protocols and network services without changes in the underlying hardware. Routers with general-purpose processors can perform data path packet processing using software that is dynamically distributed. However, custom processing of packets at link speeds on a high performance router requires immense computational power. Single workstation ...