In regular FIR structure, by pipelining the multipliers one can improve the throughput. But as the growth of operand word length, the delay in addition process becomes another important constraint. In this paper, a novel fine-grain pipelining scheme for high throughput FIR is proposed. By pipelining multipliers and adders, very high throughput can be achieved. 2-Dimensional pipeline gating tech...

Paxos is probably the most known state machine replication protocol. Two optimizations that can greatly improve its performance are batching and pipelining. Their effectiveness depends significantly on the system properties, mainly network latency and bandwidth, but also on the CPU speed and properties of the application. This makes it hard to know when and how to use each optimization to achie...

A pipelined architecture for adaptive pulse code modulation (ADPCM) is presented. The architecture is developed by the application of relaxed fo rm of look-ahead. The hardware overhead is only the the pipelining latches and is independent of the number of quantizer levels, the predictor order and the pipelining level. The codec latency is smaller than the level of pipelining. Under the assumpti...

Wire delays and communication time are forcing processors to become decentralized modules communicating through a fast, scalable interconnect. For scalability, every portion of the processor must be decentralized, including the memory system. Compilers that can take a sequential program as input and parallelize it (including the memory) across the new processors are necessary. Much research has...

Pipelining is a widely used technique that query execution engines employ to improve individual query execution times. In recently proposed settings, pipelining is used as an alternative to materialization to evaluate query plan graphs, where nodes in a query plan can have multiple parents. Such scenarios include shared table scans, runtime operator sharing, parallel sorting, and pipelined Mult...

With the escalation of clock frequencies and the increasing ratio of wire to gate delays clock skew is a major problem to be overcome in tomorrow s high speed VLSI chips Also with an increasing number of stages switching simultaneously comes the problem of higher peak power consumption In our past work we have proposed a novel scheme called Counter ow Clocked C Pipelining to combat these proble...

In this paper a novel hybrid wave-pipelined bit-pattern associative router is presented. A router is an important component in communication network systems. The bitpattern associative router (BPARj allows for flexibility and can accommodate a lavge number of routing algorithms. Wave-pipelining is a high performance approach which implements pipelining in logic without using intermediate regist...