Co-design tools represent an effective solution for reducing costs and shortening time-to-market, when System-on-Chip design is considered. In a top-down design flow, designers would greatly benefit fiom the availability of tools able to automatically generate test sequences, which can be reused during the following design steps, from the system-level specification to the gate-level description...

Rapid and reliable test of SOCs necessitates upfront consideration of the test power issues. Special attention should be paid to scanbased cores as the test power problem is more severe due to excessive switching activity stemming from scan chain transitions during shift operations. We propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain thr...

SLE(κ, ~ ρ ) is a generalisation of Schramm-Loewner evolution which describes planar curves which are statistically self-similar but not conformally invariant in the strict sense. We show that, in the context of boundary conformal field theory, this process arises naturally in models which contain a conserved U(1) current density Jμ, in which case it gives rise to a highest weight state |h〉 sat...

The purpose of this paper is to integrate the management of power consumption to augment the parallelism of the testing activities and to reduce the testing time of SOCs. This is achieved in three parts. First, a specific scan cell is employed to reduce the switching activities during test scan stages. Secondly, a test vector reordering approach is used to reduce the test power. Finally, a test...

Dynamic regulation and packaging of genetic information is achieved by the organization of DNA into chromatin. Nucleosomal core histones, which form the basic repeating unit of chromatin, are subject to various post-translational modifications such as acetylation, methylation, phosphorylation, and ubiquitinylation. These modifications have effects on chromatin structure and, along with DNA meth...

Embedded Systems are designed for a specific task based on characterization. But in the modern advancements these are doing several tasks at a time, to achieve this it requires an operating system along with powerful processor. In this paper proposes the Board Support Packages (BSP) customization of Embedded Linux OS, especially ARM9 based Freescale Silicon Vendor platforms with the help of Lin...

A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor’s on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The pro...

The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and very efficient lossless compression technique for testing systems-on-a-chip based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode...

A new real-time obstacle avoidance method for mobile robots has been developed and implemented. This method, named the vector field histogram (VFH), permits the detection of unknown obstacles and avoids collisions while simultaneously steering the mobile robot toward the target. The VFH method uses a two-dimensional Cartesian histogram grid as a world model. This world model is updated continuo...