Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On other hand, binary circuits face a huge number interconnection wires, which results in dissipation area. Researchers introduced emerging nanodevices multiple-valued logic (MVL) as two feasible solutions to overcome challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one ...

MOSFET is the most commonly used devices in DC-DC power converters, and its performance is important to the prognosis and health management of power. The paper proposes a degradation analysis model for MOSFET in DC-DC power converters. A method for detecting the degradation of MOSFET is also introduced. Simulations have shown that the method can predict deterioration in the performance of MOSFE...

A power MOSFET linearizer is proposed for a high-voltage power amplifier (HVPA) used in high-frequency pulse-echo instrumentation. The power MOSFET linearizer is composed of a DC bias-controlled series power MOSFET shunt with parallel inductors and capacitors. The proposed scheme is designed to improve the gain deviation characteristics of the HVPA at higher input powers. By controlling the MOS...

Most aggressively scaled metal-oxide-semiconductor field-effect (MOSFET) transistors have characteristics dimensions entering now in the nanometer scale [1]. In this context, multi-gate nanowire MOSFET’s are considered as the most promising candidates for ultimate CMOS integration, because of their efficient electrostatic coupling between the surrounding gate electrode and the conduction channe...

This paper has studied drain induced barrier lowering(DIBL) for Double Gate MOSFET(DGMOSFET) using analytical potential model. Two dimensional analytical potential model has been presented for symmetrical DGMOSFETs with process parameters. DIBL is very important short channel effects(SCEs) for nano structures since drain voltage has influenced on source potential distribution due to reduction o...

This article presents the comparison of SingleGate SOI and Multi-Gate SOI MOSFETs. In the first part we have presented two main fundamental problems of the “ultimate” (sub-10-nm) MOSFET scaling of Single-Gate geometry: the exponential growth of power consumption and sensitivity to fabrication uncertainties. These factors have played the decisive role in for eventual transfer of the CMOS industr...

Variability in device characteristics will affect the scaling and integration of next generation nano-CMOS transistors. Intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness and oxide thickness fluctuations are among the most important sources of variability. In this paper the variability introduced by the above sources is studied in a set of well scaled MO...

An integrated circuit (IC) dimensions continue to decrease, RC delay, crosstalk noise, and power dissipation of the interconnect structure become limiting factors for ultra-large-scale integration of integrated circuits. Modern microcircuits may have eight metal layers, each separated by only 0.1 micrometers. RC delays and cross talk rather than transistor speed are now the major performance li...

Non-equilibrium Green’s function (NEGF) is a general method for modeling non-equilibrium quantum transport in open mesoscopic systems with many body scattering effects. In this paper, we present a unified treatment of quantum device boundaries in the framework of NEGF with both finite difference and finite element discretizations. Boundary treatments for both types of numerical methods, and the...

This paper discusses the effects of MOSFET threshold voltage variations on the reliability of nanometer-scale CMOS logic gates. The reliability is quantified in terms of the probability-of-failure of individual CMOS gates, which is obtained from extensive Monte Carlo simulations of these gates. The study considers different nano-scale CMOS technology generations and compares the effect of thres...