On-chip interconnection networks or Network-onChips (NoCs) are becoming the de-facto scaling communication techniques in Multi-Processor System-on-Chip (MPSoC) or Chip Multiprocessor (CMP) environment. However, the current traffic models for on-chip interconnection networks are insufficient to capture the traffic characteristics as well as evaluate the network performance. As the technology sca...

This paper develops theoretical support useful for determining deadlock properties of dynamic network reconfiguration techniques and also serves as a basis for the development of design methodologies useful for deriving deadlock-free reconfiguration techniques. It is applicable to interconnection networks typically used in multiprocessor servers, network-based computing clusters and distributed...

This paper deals with the minimization of inter-task and inter-processor communication costs in the context of one SQL query mapping onto a sharednothing architecture, as far as the parallel decisional query processing is concerned. After setting both the models of the application handled and the target multiprocessor architecture, a study aimed at minimizing both inter-processor transfer times...

Space-Based Radar (SBR) processing is a processorand communication-intensive HPEC application that presents unique design challenges. This talk will concentrate on the presentation of simulation results of mapping a parallel Ground Moving Target Indicator (GMTI) application on an embedded multiprocessor satellite processing system featuring a RapidIO interconnection network. We consider three p...

Multiprocessor systems on chip (MPSoC) designs are increasingly being used in today’s embedded system, to follow phenomenal increase of embedded products performance requirements. In these systems one of the most critical components regarding overall efficiency is on-chip interconnections which have a great impact on the performance constraints of modern MPSOC. Multistage interconnection networ...

In this paper, we examine WiMAX – based network and evaluate the performance for quality of service (QoS) using an idea of IEEE 802.16 technology. In our models, the study used a multiprocessor architecture organized by the interconnection network. OPNET Modeler is used to simulate the architecture and to calculate the performance criteria (i.e. throughput, delay and data dropped) that slightly...

The Batcher-Banyan (BB) network is an important class of non-blocking multistage interconnection networks widely used in shared memory multiprocessor interconnection and as well as in ATM switches. In this project, we implemented switching elements for these Batcher-Banyan networks. These switches were designed to be fully scalable so that the same switching element could be used for building l...

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohib...

Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based mult...

This section introduces basic switching techniques used within the routers of multiprocessor interconnection networks. Switching techniques determine when and how messages are forwarded through the network. These techniques determine the granularity and timing with which resources such as buffers and switch ports are requested and released and consequently determine the blocking behavior of rou...