Smart grid endpoints need to use two environments within a processing system (PS), one with Linux-type operating (OS) using the Arm Cortex-A53 cores for management tasks, and other standalone execution or real-time OS Cortex-R5 cores. The Xen hypervisor OpenAMP framework allow this, but they may introduce delay in system, some messages smart latency lower than 3 ms. In this paper, Linux thread ...

Tango is a software simulation and tracing system used to obtain data for evaluating parallel programs and multiprocessor systems. The system provides a simulated multiprocessor environment by multiplexing application processes onto a single processor. Tango achieves high efficiency by running compiled user code, and by focusing on the information of greatest interest to multiprocessing studies...

A method for superimposing voltage sources is sought optimized by using a sparse triangular solver and multiprocessing. A revision to the method is suggested which exploits Schur’s complement of the network admittance matrix and optimal re-use of computations. The algorithm is implemented and parallelized for shared memory multiprocessing. The proposed algorithm is tested on a collection of lar...

Nowadays, multi-core processors are widely used in embedded applications due to the advantages of higher performance and lower power consumption. However, the complexity of multi-core architectures makes it a considerably challenging task to extend a single-core version of a real-time operating system to support multi-core platform. This thesis documents the process of design and implementation...

The AlphaServer 2100 I/O subsystem contains a dual-level I/O structure that includes the high-powered PCI local bus and the widely used EISA bus. The PCI bus is connected to the server's multiprocessing system bus through the custom-designed bridge chip. The EISA bus supports eight general-purpose EISA/ISA connectors, providing connections to plug-in, industry-standard options. Data rate isolat...

Computer parently reordering instructions from nearby program regions, but even sophisticated compiler scheduling is fundamentally limited by the compiler’s inability to perfectly determine the programmer’s intent and its commitment to preserve the program’s high-level structure and semantics. Given the amount of parallel work being done, we could conceivably build a superscalar processor with ...