A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and...

This paper presents the LIG contribution to the CLEF 2007 medical retrieval task (i.e. ImageCLEFmed). The main idea in this paper is to incorporate medical knowledge in the language modeling approach to information retrieval (IR). Our model makes use of the textual part of ImageCLEFmed corpus and of the medical knowledge as found in the Unified Medical Language System (UMLS) knowledge sources. ...

A general discussion on combining statistical hypothesis tests is followed by an application involving point source detection in skymaps. The traditional literature on combining statistical tests has concentrated on a regime in which p-values as large as 0.05 are still of interest, and in which it is dangerous to treat tests as truly independent. But for point source detection, very small p-val...

Many studies have noted significant differences among human electroencephalograph (EEG) results when participants or patients are exposed to different stimuli, undertaking different tasks, or being affected by conditions such as epilepsy or Alzheimer's disease. Such studies often use only one or two measures of complexity and do not regularly justify their choice of measure beyond the fact that...

This letter proposes a parasitic elimination bootstrapped switch and fast settling residual amplifier to be used in multiplying digital-to-analog converter (MDAC) order improve the performance of pipelined ADC at high frequency. The improves sampling spurious free dynamic range (SFDR) by more than 6dB shielding nonlinear capacitance MOS transistor substrate. In addition, frequency, negative zer...

A pipelined analog-to-digital converter (ADC) has been investigated, which has a programmable gain achieved by the gain control in a first-stage multiplying digital-to-analog converter (MDAC). The current consumption reduction under low gain is realized by controlling the transconductance and compensation capacitor of the MDAC circuit according to the input gain. The pipelined ADC designed usin...