Due to their potential to deliver increased performance over single-core processors, multi-core processors have become mainstream in processor design. Computation-intensive real-time systems must exploit intra-task parallelism to take full advantage of multi-core processing. However, existing results in real-time scheduling of parallel tasks focus on restrictive task models such as the synchron...

Abstract: This paper proposes a novel scheme for multi-static passive radar processing, based on soft-input soft-output processing and Bayesian sparse estimation. In this scheme, each receiver estimates the probability of target presence based on its received signal and the prior information received from a central processor. The resulting posterior target probabilities are transmitted to the c...

Scientific computations for diffusion equations and ANNs (Artificial Neural Networks) are data intensive tasks accompanied by heavy memory access; on the other hand, their computational complexities are relatively low. Thus, this type of tasks naturally maps onto SIMD (Single Instruction Multiple Data stream) parallel processing with distributed memory. This paper proposes a high performance ac...

Applications such as image processing, uid mechanics, and geophysical data analysis are examples of problems that require the high computing performance provided by multi-processor systems. Such performance depends highly on the inter-processor communication time resulting from the allocating tasks to the individual processors. This research focuses on the development of techniques that reduce ...

Internet Security (IPSEC) protocol is part of a design consideration in Virtual Private Networks (VPN). In this paper, we design and implement a 10 Gbit/s gateway router for IPSEC processing using the Intel network processor IXP2850. In particular, using software and hardware partitioning on a complex multi processor system, i.e., selecting appropriate processors to offload computational intens...

According to the increasing complexity of network application and internet traffic, network processor as a subset of embedded processors have to process more computation intensive tasks. By scaling down the feature size and emersion of chip multiprocessors (CMP) that are usually multi-thread processors, the performance requirements are somehow guaranteed. As multithread processors are the heir ...

Concurrency is an attractive property of a language to exploit multi-CPU hardware or perform multiple tasks concurrently. In recent years we see Prolog systems experimenting with multiple threads only sharing the database. Such systems are relatively easy to build and remain very close to standard Prolog while providing valuable extra functionality. This article describes the introduction of mu...

We present the i-Core (Invasive Core), an Application Specific Instruction Set Processor (ASIP) with a run-time adaptive instruction set. Its adaptivity is controlled by the runtime system with respect to application properties that may vary during run-time. A reconfigurable fabric hosts the adaptive part of the instruction set whereas the rest of the instruction set is fixed. We show how the i...

An energy efficient pipelined architecture is proposed for multi-core object recognition processor. The proposed neuro-fuzzy controller and intelligent estimation of the workload of input video stream enable seamless pipelined operation of the 3 object recognition tasks. The neuro-fuzzy controller extracts the fine-grained region-of-interest, and its task pipelining achieves 60.6fps, 5.8x highe...