n September 1994, Digital Equipment Corporation introduced the 21164 Alpha microprocessor. This processor exceedU ed the performance level o f existing Alpha microprocessors by over 50 percent and delivered exceptional Performance on computing-intensive applications such as large database manipulation, scientific and technical simulation, CAD, and powerful user interfaces. The first microproces...

Microprocessor core counts are on a trajectory such that for many applications the microprocessor will soon be overprovisioned for computation with respect to off-chip communication and memory system capabilities. In the absence of strategies to exploit intra-chip communication, performance of even simple benchmarks is noticeably impacted by coscheduling multiple copies on the cores of current ...

This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token at the most likel...

The papers for this special issue of Computer were selected to be representative of those presented at the DISE Workshop on Microprocessors and Education held at Colorado State University, August 16-18, 1976. The workshop was sponsored by the DISE Committee (Digital Systems Education Committee-a project supported by the National Science Foundation) along with the Departments of Electrical Engin...

When designing embedded systems, one needs to make decisions concerning the different components that will be included in a microprocessor. An important issue in this phase is the chip area vs. performance tradeoff. In this paper we investigate the relationship between chip area and performance for superscalar microprocessors. We evaluate how one can obtain a suitable configuration by using an ...

The S/390@ floating-point unit (FPU) on the fourth-generation (G4) CMOS microprocessor chip has been implemented in a CMOS technology with a 0.20-pm effective channel length and has been demonstrated at more than 400 MHz. The microprocessor chip is 17.35 by 17.30 mm in size, and one copy of the FPU including the dataflow and control flow but not including the FPR register file is 5.3 by 4.7 mm ...

As more transistors are integrated onto larger dies, single-chip multiprocessors integrated with large amounts of cache memory will soon become a feasible alternative to the large, monolithic uniprocessors that dominate today’s microprocessor marketplace. Hydra offers a promising way to build a small-scale MP-on-a-chip using a fairly simple design that still maintains excellent performance on a...

POWER5 microprocessor and POWER5 multiprocessor systems D. W. Victor J. M. Ludden R. D. Peterson B. S. Nelson W. K. Sharp J. K. Hsu B.-L. Chu M. L. Behm R. M. Gott A. D. Romonosky S. R. Farago This paper describes the methods and simulation techniques used to verify the functional correctness and performance attributes of the IBM POWER5e microprocessor and the eServere p5 systems based on it. T...