Hardware-assisted garbage collection offers the potential of high average-case allocation rates and memory bandwidth, with very low worst-case allocation, fetch, and store times. This paper describes an architecture that allows memory fetch and store operations to execute, on the average, nearly as fast as traditional memory. The architecture is high-performance in that it includes support for ...

Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizations fo r programmable systems assumed a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for the application. Howevel; such a processormemory eo-expl...

Clock acceleration and ILP extraction have drastically improved processor performance. However, performance of memory has not been improved so much as that of processor, thus the problem of performance gap between memory and processor, which is called memory wall problem, is becoming very serious. This will get more serious in the near future. We propose a new VLSI architecture which can solve ...

Distributed-memory multiprocessor architecture is essential in developing massively parallel machines. One of the most important design issues in such a distributed-memory multiprocessor architecture is a latency problem which is caused by remote procedure invocation and remote memory access. Remote memory access and remote procedure invocation occur so often in massively parallel execution, an...

Emerging non-volatile memory (NVM) technologies, such as PCRAM and STT-RAM, are getting mature in recent years. These emerging NVM technologies have demonstrated great potentials to be the candidates for future computer memory architecture design. It is important for SoC designers and computer architects to understand the benefits and limitations of such emerging memory technologies, to improve...

this paper presents a modified 32-bit rom-based direct digital frequency synthesizer (ddfs). maximum output frequency of the ddfs is limited by the structure of the accumulator used in the ddfs architecture. the hierarchical pipeline accumulator (hpa) presented in this paper has less propagation delay time rather than the conventional structures. therefore, it results in both higher maximum ope...

Despite its dominance, object-oriented computation has received scant attention from the architecture community. We propose a novel memory architecture that supports objects and garbage collection (GC). Our architecture is co-designed with a Java Virtual Machine to improve the functionality and efficiency of heap memory management. The architecture is based on an address space for objects acces...

We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with ...

A prototypical cognitive architecture defines a memory architecture embodying forms of both procedural and declarative memory, plus their interaction. Reengineering such a dual architecture on a common foundation of graphical models enables a better understanding of both the substantial commonalities between procedural and declarative memory and the subtle differences that endow each with its o...