To find the proper solutions for test power reduction strategy for parallel core-based SoC, in this paper, starting from the terminology and models for power consumption during test, The efforts to reduce the power consumption during normal function mode further exaggerated the power consumption problem during test. The state of the art in low-power testing is presented, various power reduction...

due to the high density and the low consumption power in the digital integrated circuits, mostly technology of cmos is used. during the past times, the metal oxide silicon field effect transistors (mosfet) had been used for the design and implementation of the digital integrated circuits because they are compact and also they have the less consumption power and delay to the other transistors. b...

Adders are the basic building block in the arithmetic circuits. In order to achieve high speed and low power consumption a 32bit carry skip adder is proposed. In the conventional technique, a hybrid variable latency extension is used with a method called as parallel prefix network (Brent-Kung). As a result, larger delay along with higher power consumption is obtained, which is the main drawback...

One of the obstacles preventing the Zigbee protocol from being widely used is the excessive power consumption of Zigbee devices in low bandwidth and low power requirement applications. This paper proposes a protocol that resolves the power efficiency problem. The proposed protocol reduces the power consumption of Zigbee devices in beacon-enabled networks without increasing the time taken by Zig...

Low-power wireless networks are quickly becoming a critical part of our everyday infrastructure. Power consumption is a critical concern, but power measurement and estimation is a challenge. We present Powertrace, which to the best of our knowledge is the first system for network-level power profiling of low-power wireless systems. Powertrace uses power state tracking to estimate system power c...

0038-1101/$ see front matter 2008 Elsevier Ltd. A doi:10.1016/j.sse.2008.06.045 * Corresponding author. Tel.: +32 10 47 8134; fax: E-mail addresses: [email protected] (D. Bo vain.be (R. Ambroise), [email protected] ( [email protected] (J.-D. Legat). For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high ...

today power consumption is considered to be one of the important issues. therefore, its reduction plays a considerable role in developing systems. previous studies have shown that approximately 50% of total power consumption is used in cache memories. there is a direct relationship between power consumption and replacement quantity made in cache. the less the number of replacements is, the less...

Due to the high density and the low consumption power in the digital integrated circuits, mostly technology of CMOS is used. During the past times, the Metal oxide silicon field effect transistors (MOSFET) had been used for the design and implementation of the digital integrated circuits because they are compact and also they have the less consumption power and delay to the other transistors. B...