The paper reports the implementation of address generator of the 2-D deinterleaver used in wimax transreceiver system using FPGA. The bit streams in channel interleaver and deinterleaver for IEEE 802.16e standard associated with floor function is very difficult to implement on the FPGA kit. But by using this proposed algorithm eliminates the requirement of floor function and it also reduces the...

This paper presents an efficient implementation of Finite Impulse Response Filter (FIR) using Distributed Arithmetic (DA) architecture. Here, the multipliers in FIR filter are replaced with multiplierless DA based technique. The DA based technique consists of Look Up Table (LUT), shift registers and scaling accumulator. Analysis on the performance of various filter orders with various partition...

We propose high speed architecture for Keccak using Look-Up Table (LUT) resources on FPGAs, to minimize area of Keccak data path and to reduce critical path lengths. This approach allows us to design Keccak data path with minimum resources and higher clock frequencies. We show our results in the form of chip area consumption, throughput and throughput per area. At this time, the design presente...

This paper presents an investigation of Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using various architectures of the Inverse Discrete Cosine Transform (IDCT). To compare FPGA architectures of different vendors, a generic FPGA model is developed and used in architecture independent modelling software. LUTs with three inputs yield the best results in terms of area when mapp...

In this paper, we describe a modular reconfigurable architecture for efficient stuck-at fault simulation in digital circuits. The architecture is based on a Universal Faulty Gate Block, which models each 2-input gate by a 4-input Look-Up Table (LUT) and a Shift-Register (SR) with 3 stages, and relies on colapsing the stuck-at fault list of the gates using equivalence and dominance relations bet...

Field Programmable Gate Arrays (FPGA’s) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD’s) for selecting good lambda set variables in Roth-Karp decomposition to minimize the numbe...

Leaf area index (LAI) is a key variable for modeling energy and mass exchange between the land surface and the atmosphere. Inversion of physically based radiative transfer models is the most established technique for estimating LAI from remotely sensed data. This study aims to evaluate the suitability of the PROSAIL model for LAI estimation of three typical row crops (maize, potato, and sunflow...

The proposed work is to analyze the power consumption of Finite Impulse Response (FIR) filter under different combinatorial modules. Under the considered modules namely Parallel, serial and Distributed Arithmetic(DA) architectures, effects of variation of clock frequency, leakage capacitance, supply voltage are chosen to determine power consumption and junction temperature. Each module is simul...

In this paper we propose an efficient pipelined architecture for low power,high throughput and low area adaptive FIR filter based on distributed airthemetic. The throughput rate is significantly increased by parallel look-up table(LUT) update. Reduction in power consumption is achieved by using a fast bit clock for carry save accumulation. We have shown that sampling period could be sequentiall...