In this paper we will present a formal framework, based on the notion of extraction calculus, which has been successfully applied to define procedures for extracting information from constructive proofs. Here we will apply such a mechanism to give a proof-theoretic account of SLD-derivations. We show how proofs of suitable constructive systems can be used in the context of deductive synthesis o...

This paper shows the best operators for sumof-products expressions. We first describe conditions of functions for product and sum operations. We examine all two-variable functions and select those that meet the conditions and then evaluate the number of product terms needed in the minimum sum-of-products expressions when each combination of selected product and sum functions is used. As a resul...

Abstmct-While the use of programmable logic arrays in modern logic design is common, little is known about what PLA size provides reasonable coverage in typical applications. We address this question by showing upper and lower bounds on the average number of product terms required in the minimal realization of binary and multiple-valued functions as a function of the number of nonzero output va...

Memristors can be used as logic gates. No design methodology exists, however, for memristor-based combinatorial logic. In this paper, the design and behavior of a memristivebased logic gate – an IMPLY gate are presented and design issues such as the tradeoff between speed (fast write times) and correct logic behavior are described, as part of an overall design methodology. A memristor model is ...

In the paper a method of logic synthesis of one-stage digital circuits on the base of Generic Array Logic (GAL) is proposed. Unlike the traditional approach to the logic synthesis on PLD, this method takes in account special internal resources and architectural features of GAL structures at the earliest stages of project design that allows increase the efficiency of logic synthesis. The conditi...

Phased logic is a synthesis/mapping methodology that allows a standard clocked netlist (combinational gates + DFFs) to be automatically mapped to a non-clocked netlist that uses special gates called phased logic gates. The new netlist has no clock networks and the only required global signal is a power-on reset. We demonstrate the viability of the phased logic approach via the synthesis and sim...

Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) in some specialized areas due providing ultra-fast and energy-efficient circuits. To realize large-scale integration design, electronic design automation (EDA) tools for RSFQ are required the divergences type, timing constraints, circuit structure compared with CMOS logic....

In this paper we suggest measures for making the synthesis process more likely to succeed. As a first measure the synthesis task must be made intelligible by making the starting point, the way of reasoning, and criterion for conclusion of the synthesis clear. Secondly, the interactive synthesis process can be supported by a planning ingredient in the system as a way for the system and the user ...

A methodology to optimize handshake circuits is presented. The approach selects clusters of the initial handshake network for which signals representing internal channels within a cluster are hidden. To guarantee asynchronous implementability on the resulting cluster, state encoding is applied using modern structural techniques. The theory of Petri nets is used to identify clusters for which th...

A dynamic texture (DT) refers to a sequence of images that exhibit temporal regularities and has many applications in computer vision and graphics. Given an exemplar of dynamic texture, it is a dynamic but challenging task to generate new samples with high quality that are perceptually similar to the input exemplar, which is known to be example-based dynamic texture synthesis (EDTS). Numerous a...