An important goal for synthetic biology is to build robust and tunable genetic regulatory networks that are capable of performing assigned operations, usually in the presence of noise. In this work, a synthetic gene network derived from the bacteriophage λ underpins a reconfigurable logic gate wherein we exploit noise and nonlinearity through the application of the logical stochastic resonance ...

Reversible logic is one of the emerging technologies having promising applications in quantum computing. This project will deal with the design of a 16 bit reversible Arithmetic Logic Unit (ALU) with 15 operations is presented by making use of Double Peres gate, Fredkin gate, Toffolli gate, DKG gate and NOT gate. A new VLSI architecture for ALU using reversible logic gates is proposed. ALU is o...

ABSTRACT In this paper we propose Double gate transistors (FinFETs) are the substitutes for bulk CMOS evolving from a single gate devices into three dimensional devices with multiple gates (double gate, triple gate or quadruple-gate devices). The main drawback of using CMOS transistors are high power consumption and high leakage current. Enormous progress has been made to scale transistors to e...

This paper investigates the design of deeply pipelined synchronous circuits with stateful logic, which can be implemented with several recently suggested emerging device technologies. Stateful logic is well suited for high-throughput processing because each gate combines logic and memory functionality. The downside of the high throughput computation is that all logic paths must have equal lengt...

Quantum dot cellular Automata (QCA) is leading technology for alternative of CMOS design. Reversible Logic design is found to be Low power design which becomes emerging technology in Low power Nanotechnology era. In this work we devoted to design a Reversible Logic Gate which is a universal gate (known as URLG) and can be design with alternative of co-planer cross over wire. We introduce a pass...

Memristors can be used as logic gates. No design methodology exists, however, for memristor-based combinatorial logic. In this paper, the design and behavior of a memristivebased logic gate – an IMPLY gate are presented and design issues such as the tradeoff between speed (fast write times) and correct logic behavior are described, as part of an overall design methodology. A memristor model is ...

We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p-and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45nm high-performance logic technology node. 1. Introduction The silicon industry has been scaling SiO2 aggressively for the past 15 years for low-power,...

[5] C. R. Edwards, "A special class of universal logic gate, and their evaluation under the Walsh transform," Int.A consideration of the minimum number of input terminals on universal logic gates, and their realization," Int. J. We would like to thank Hurst for his interest in our correspondence. His comments are addressed to the topic of U.L.M. realization, which has been the subject of consid...

Testable fault tolerant system design has become vital for many safety critical applications. On the other hand, reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. Any Boolean logic function can be implemented using reversible gates. This paper proposes a technique to convert any reversible logic gate to a testable gate that is also reversi...

Every user of programmable logic at some point faces the question: “How large a device will I require to fit my design?” In an effort to provide guidance to their users, Field Programmable Gate Array (FPGA) manufacturers, including Xilinx, describe the capacity of FPGA devices in terms of “gate counts.” “Gate counting” involves measuring logic capacity in terms of the number of 2-input NAND gat...