Pipelined FPGAs promise high performance for reconfigurable computing. However, the architectural design of these systems is complex, involving the optimization of numerous features. In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, regist...

On-chip interconnect delays are becoming an increasingly important factor for high-performance microprocessors. Consequently, critical on-chip wiring must be carefully optimized to reduce and control interconnect delays, and accurate interconnect modeling has become more important. This paper shows the importance of including transmission line effects in interconnect modeling of the on-chip clo...

We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and flip-flop placement problem as a local area constrained retiming problem and solve it as a series of weighted minimum area retiming problems. Our method for early interconnect planning can reduce and even avoid design iter...

A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagne...

With processor and memory technologies pushing the performance limit, the bottleneck is clearly shifting towards the system interconnect. Any solution that addresses PCI’s bus-based interconnect, which has serious scalability problems, must also protect the huge legacy infrastructure. PCI Express provides such an evolutionary approach and allows a smooth migration towards building a highly scal...

In this paper we discuss generating low order models for efficient coupled circuitinterconnect simulation. The ever increasing speeds and shrinking feature sizes that are typical of state of the art integrated circuits designs have made coupling due to interconnect and packaging a very important, sometimes dominant, factor in system performance. The ability to efficiently perform coupled circui...

We introduce a scalable interconnect for workstations which uses crossbar switches and serial links. Connected to the interconnect are nodes such as I/O devices and processor/memory modules. Communication is based on load and store operations rather than on message passing, that is, all cluster memories reside in a single address space, and all locations are accessed in a uniform manner. This p...

This paper explores the use of interconnect signaling techniques to improve Delay time for performance and reduce power consumption of On-chip interconnect. The various Driver–Receiver pairs such as ddc-db, asf-lc, mj-sib and mj-db for On-chip interconnect with different capacitive load at the output of the circuit are being explored in detail. A detailed comparison of the driver-receiver pairs...

In electromigration degradation process the existing physical defects on interconnect play a critical role by significantly accelerating the EM damage under increased current density and elevated temperature. In this work the simulation models were upgraded in the IC reliability simulator ARET to incorporate the effect of interconnect physical defects in expected lifetime prediction. Then based...

This paper explores the use of interconnect signaling techniques to improve Delay time for performance and reduce power consumption of On-chip interconnect. The various Driver–Receiver pairs such as ddc-db, asf-lc, mj-sib and mj-db for On-chip interconnect with different capacitive load at the output of the circuit are being explored in detail. A detailed comparison of the driver-receiver pairs...