This paper presents techniques to integrate the use of variable-latency units in a high-level synthesis (HLS) design methodology. Components used as building blocks (e.g., functional units) in conventional HLS techniques are assumed to have fixed latency values. Variable-latency units exhibit the property that the number of cycles taken to compute their outputs varies depending on the input val...

This paper presents an approach to synthesis of hardware systems specified as interacting VHDL processes. Different from traditional high-level synthesis methodologies our approach takes into account the interactions and interdependence between concurrent processes. Two methods have been developed. The first method supports an unrestricted use of signals and wait statements and synthesizes sync...

This paper discusses a program synthesis system to facilitate the generation of high-performance parallel programs for a class of computations encountered in quantum chemistry and physics. These computations are expressible as a set of tensor contractions and arise in electronic structure modeling. An overview is provided of the synthesis system under development, that will take as input a high...

In everyday life, people use a large diversity of hands configurations while reaching out to grasp an object. They tend to vary their hands position/orientation around the object and their fingers placement on its surface according to the object properties such as its weight, shape, friction coefficient and the task they need to accomplish. Taking into account these properties, we propose a met...

In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synt...

The Princeton University Behavioral Synthesis System (PUBSS) is a high-level synthesis system targeted to control-dominated machines. PUBSS accepts a VHDL subset, in which the design can be described as multiple communicating processes plus registers, and generates a register-transfer implementation. This paper describes the compiler with emphasis on the automaton-based algorithms which allow e...

The recent emerging of commercial high-level synthesis tools raises the question of specifying IPs at the algorithmic, or behavioral, level. High-level synthesis allows fast exploration of various architectural solutions from a single behavioral description. While flexibility of currently used soft IPs is limited to optimizing the logic synthesis flow, behavioral IPs introduce architectural fle...

Classical strategies in design for testability are applied at the gate-level, after the RT-logic synthesis process. New techniques covering test and synthesis (Test Synthesis) [1] are appearing but their application is mainly oriented to gate level (commercial tools such as Synopsys). On the other hand, most high-level synthesis tools do not take into account the testability of the final archit...

This work has attempted to exploit information sharing to improve the results of Adaptive Simulated Annealing 1] as an optimization algorithm of the high-level synthesis of testable data paths. We have used Messengers 3] as a coordination tool to run several parallel instances of the annealing algorithm on the same design with diierent probability arrays for the perturbations. When all these in...