In this paper, we present a new methodology towards performing high-level synthesis. During high-level synthesis an algorithmic description is mapped to a structure of hardware components. In our approach, high-level synthesis is performed via program transformations. All transformations are performed within a higher order logic theorem prover thus guaranteeing correctness. Our approach is not ...

This paper presents the behavioural synthesis of a complex application widely used in digital communications : the Viterbi algorithm. Since architectural synthesis allows different design alternatives to be rapidly explored under various constraints, dedicated architectures can be generated. In the same way, when the behavioural specification is generic, the synthesis can be rapidly turned to a...

In this paper a flexible interface to high-level synthesis data (NEAT) is presented. NEAT offers three design views to common high-level synthesis data domains. Interand intra-domain relations are used to represent design relations between synthesis objects and to store synthesis results. To extend the functionality of the common synthesis interface programmers use object oriented programming t...

Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the performance impact of including such devices into design when using traditional design methods and tools. In this paper, we present easily adaptable system-level techniques, which are able to perform fast exploration of dif...

This paper presents an approach to back-annotation of timing information in behavioral VHDL descriptions. In our approach, a behavioral VHDL description specifies the functionality and timing constraints of a design which is synthesized by a high-level synthesis tool. After synthesis the timing information of the design is back-annotated to the original VHDL description which is then used for s...

Many high level synthesis systems produce designs without any consideration for the underlying architecture. In such systems, tradeo s between area and delay can only be achieved by changing the synthesis constraints (e.g., number of functional units). These systems do not exploit the wider range of tradeo s that can be achieved by modifying the underlying architecture. In this report we derive...

This paper presents a method to carry out the register allocation/binding phase of a High Level Synthesis flow with testability considerations. Testability problems are identified at behavioral level and are eliminated as much as possible during this phase turning testability/area trade-off to account. Proposed method is based on high level normalized testability measures, it allows to improve ...

Scheduling is one of the main problems that need to be solved by high-level hardware and software compilers. Existing heuristics are often incapable of finding feasible solutions for practical examples, because the tight time and resource constraints make the feasible-solution subspace very small compared to the size of the full search space. For that reason, constraint-analysis techniques that...

One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the results are usually checked by simulation. In consequence, both the behavioral specification and the HLS results have to be simulated by the same set of test vectors. Due to the HLS and the inherent changes in the cycle-b...

This application note discusses various design techniques for implementing resampling filters using the Altera® DSP Builder advanced blockset. The DSP Builder advanced blockset supports constraint-based high-level synthesis and is particularly efficient for implementing multiple channel, high-performance resampling filters. You can use the DSP Builder advanced blockset to quickly map highly abs...