Safety-critical systems have to be fault tolerant and also meet stringent temporal constraints. Various redundancy strategies are built into such mission-critical applications to ensure the overall success of the mission. This paper implements a fault tolerant scheduling scheme on a dual processor system, wherein the redundancy is made at the task level. The system continues to function with gr...

The advent of reconfigurable hardware as a computing medium creates a multi-dimensional design space where trade-offs between power, speed, cost, and reliability are now possible. Dynamic reconfiguration allows these trade-offs to be made on-line to adapt to various environmental changes. Furthermore, the cost of designing reliable circuits is greatly reduced since varying levels of reliability...

We consider teams of mobile autonomous robot systems that coordinate their work via communication over a wireless local area network. In such a scenario, timely delivery and group support are the predominant requirements on the communication protocol. As the mobile robot systems are communicating via standard hardware, we base our work on the IEEE 802.11 standard for wireless local area network...

The safety of electric vehicles has the highest priority because it helps contribute to customer confidence and thereby ensures further growth of the electromobility market. Therefore in series production redundant hardware concepts like dual core microcontrollers running in lock-step-mode are used to reach ASIL D safety requirements given from the ISO 26262. Coded processing is capable of redu...

the redundancy allocation problem can be described as selecting the components and system configuration in order to optimize some objective function(s) without violating the system constraints. operating conditions are not constant in many advanced engineering systems. mostly, in the engineering applications selection, the number of redundancy components must be balanced among the constraints (...

Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional field-programmable gate arrays (FPGAs) since they efficiently reuse limited hardware resources in time. One of the typical DPGA architectures is a multi-context FPGA (MC-FPGA) that requires multiple memory bits per configuration bit to realize fast context switching. However, this additional memory...

A recent sigma-delta modulator architecture incorporates spectral shaping of hardware-mismatch errors through redundancy introduced by embedding the input/output subspace in a higher-dimensional space for loop operation. Here basic design issues for the key vector quantizer and matriximpulse-response loop filter are explored. A simple design example and simulation illustrate.

In this paper, we propose a High Availability Open Shortest Path First (HA-OSPF) router which consists of two OSPF router modules, active and standby, to support a high availability network. First, we used the continuous-time Markov chain (CTMC) to analyze the steady-state availability of an HA-OSPF router with one active router and N standby routers (1 + N redundancy model). Then, with the fai...

This paper describes different schemes for tolerating faults in augmented hypercube multiprocessors. The architectures considered have a spare assigned to each subset of nodes (cluster). The approaches make use of hardware redundancy in the form of spare nodes and/or links and usually requires modifications in the communication as well as computation algorithms.

We propose a new generic modeling framework, with validating hardware experiments, for hyper-modular mechanisms and robots (tens to thousands of modules) which may exhibit extreme redundancy and parallelism. Our framework efficiently captures the second-order effects of dimensional tolerance and uncertain mechanical play and flexibility, and helps enable efficient actuator cooperation for force...