Received Nov 21, 2017 Revised Jan 29, 2018 Accepted Feb 17, 2018 In the field of Digital signal processing (DSP), the reduction of some logical elements counts is one of the main considerations. To minimize the area, computational delay, and power, the digital form FIR filter is to be implemented. The optimization of the ATP (Area, Time and Power) is achieved by using the efficient multiplicati...

Based on an algorithm derived from the New Chinese Remainder Theorem I, we present three new residue-to-binary converters for the residue number system (2 1 2 2 + 1) designed using 2 -bit or -bit adders with improvements on speed, area, or dynamic range compared with various previous converters. The 2 -bit adder based converter is faster and requires about half the hardware required by previous...

Some arithmetical operations on binary (or 2s complement) numbers performed on Cellular Automata (CA) are presented: a) by implementing on the CA the half-adder functions it is possible to perform a pipelined binary addition of binary number pairs which gives results every two machine-state transitions (after the start-up phase); b) by implementing the full-adder functions on the CA, the sum of...

One of the most important tasks in design and manufacturing of integrated circuits is the testing phase. Distinguishing between faulty and fault free ICs is a difficult task Therefore, simulations are being done for different circuits to identify fault free and faulty circuits. The circuits include analog circuits, digital circuits &mixed signal circuits. Analog circuits like Low pass filter, H...

In high speed applications, multipliers and their associated circuits like accumulators, half adders, and full adders consume a significant portion. Therefore, it is necessary to increase their performance as well as size efficiency. In order to reduce the hardware complexity which ultimately reduces an area and power, energy efficient full adders plays crucial role in Wallace tree multiplier. ...

In this paper, our main focus is to reduce computation delay proposed in previous FFA algorithm based FIR digital filter. Parallel FIR filter structure with fast finite-impulse response (FIR) along with symmetric coefficients reduces the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. . The proposed parallel FIR structures exploit the inherent nature of symme...

In this manuscript, an unusual adaptive FIR filter using distributed arithmetic (DA) for area efficient design is implemented. DA is bit-serial computational action and uses parallel look-up table (LUTs) apprise and equivalent implementation of filtering and weight-update operations to appliance high throughput filter rates irrespective of the filter length. The full adder based conditional sig...