AbstractIn today’s world everyday a new technology which is faster, smaller and more complex than its predecessor is being developed. The increased number of transistors packed onto a chip of a conventional system results in increased power consumption that is why Reversible logic has drawn attention of Researchers due to its less heat dissipating characteristics. Reversible logic can be impose...

By a combination of graphene oxide and DNA, a universal platform was developed for integration of multiple logic gates to implement both half adder and half subtractor functions. A constant undefined threshold range between high and low fluorescence output signals was set for all the developed logic gates.

The feasibility of Quantum Computer with Super Computing capability is addressed here. We describe a Arithmetic Logic Unit for Quantum Computer and show how the algebra is modified if the information is kept in phase for Radix-4 operation. We formulate Quaternary adder, subtractor, multiplier and divider circuits using basic quantum gates.

The articles [17], [16], [21], [15], [3], [18], [25], [1], [9], [10], [4], [8], [2], [19], [24], [14], [20], [13], [12], [11], [23], [5], [7], and [22] provide the terminology and notation for this paper. Let n be a natural number and let x, y be finite sequences. The functor n-BitSubtracterStr(x, y) yields an unsplit non void strict non empty many sorted signature with arity held in gates and ...

An algorithm for a fast decimal addition is proposed. The addition is performed in two steps. First, the result of addition is produced in a decimal signed-digit format. Second, the decimal signed-digit result is converted into the non-redundant form BCD. The conversion uses a borrow generating scheme based on a parallel-prefix network. Using the flexible features of the decimal signed-digit re...