The Full Adders (FAs) constitute the essential elements of digital systems, in a sense that they affect the circuit parameters of such systems. With respect to the MOSFET restrictions, its replacement by new devices and technologies is inevitable. QCA is one of the accomplishments in nanotechnology nominated as the candidate for MOSFET replacement. In this article 4 new layouts are presente...

multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and reduce the...

Full adders are essentially used as a building block in all arithmetic, DSP and microprocessor applications. In this paper, a 15 transistor hybrid PTL-TG full adder circuit is proposed. The main objective is to provide high speed, low power, full swing operation with good drivability. The choice of logic design affects the circuit performance. The delay time depends on the number of transistors...

In this paper, two novel low-power and high-speed carbon nanotube full-adder cells in dynamic logic style are presented. Carbon nanotube field-effect transistors (CNFETs) are efficient in designing a high performance circuit. To design our full-adder cells, CNFETs with three different threshold voltages (low threshold, normal threshold, and high threshold) are used. First design generates SUM a...

In this paper, 1 bit full adder is built under a new hybrid logic (combination of PTL and CMOS logic) style, using 14 MOSFETs. Here we use 6transistor XOR-XNOR circuit to implement the full adder. This full adder offers full voltage swing at every nodes, higher density and high speed than the conventional CMOS design style. TSPICE is the simulator used for the simulation and bsim3v32 technology...

This paper presents different techniques of one bit Full adder. In every technique the main requirements are power consumption, speed and power delay product. The proposed FIN-FET technique gives the bette.r power consumption, speed and power delay product than other techniques. The proposed Fin-FET technique is compared with some of the popular adders based on the power consumption, speed and ...

A set is pair if: (Def.1) There exist sets x, y such that it = 〈x, y〉. Let us mention that every set which is pair is also non empty. Let x, y be sets. Observe that 〈x, y〉 is pair. Let us mention that there exists a set which is pair and there exists a set which is non pair. Let us observe that every natural number is non pair. A set has a pair if: (Def.2) There exists a pair set x such that x ...

With the advancement of technology, power consumption and higher speed becomes major concern for VLSI systems. In this paper, a new hybrid domino XOR is proposed and compared with existing domino XOR cell. As an application of proposed XOR cell, 1-bit full adder has been designed and compared with a full adder circuit using existing XOR cell. Both proposed designs XOR and full adder show better...

In this article we continue the investigations from [5] of verification of a design of adder circuit. We define it as a combination of 1-bit adders using schemes from [6]. n-bit adder circuit has the following structure 1st bit adder x 1 y 1 x 2 y 2 r 1 r 2 2nd bit adder nth bit adder x n y n r n As the main result we prove the stability of the circuit. Further works will consist of the proof o...