This paper presents an analysis of the stability and convergence properties of the Full Signal Range CNN model. These properties are demonstrated to be similar to those of the Chua-Yang’s model, and the I/O mapping of known applications is shown to be unaffected by the modification introduced in this new model. In this modified CNN model, the dynamic range of the cell state-variables equals the...

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CM...

cement powder size classification efficiency significantly affects quality of final product and extent of energy consumption in clinker grinding circuits. static and dynamic or high efficiency air separators are being used widely in closed circuit with multi-compartment tube ball mills, high pressure grinding rolls (hpgr) and more recently vertical roller mills (vrm) units in cement plants to c...

This paper proposes and analyses the performance of a Genetic Algorithm using two new concepts, namely a static fitness function including a discontinuity measure and a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. In both cases, experiments reveal superior results in terms of speed and convergence to achieve a solution.

A new circuit technique, referred to as the twin-transistor technique, for increasing the noise immunity of dynamic logic circuits is presented. This technique makes dynamic logic gates more tolerant to noise appearing at the gate inputs. A multiply-accumulate circuit has been designed and fabricated using a 0.35pm process to veri f y this technique. Experimental results indicate that the twin-...

In this paper, we investigate the well-known state dependent multicast routing algorithm called Least Load Multicast Routing (LLMR), for single rate loss networks. The algorithm is based on the Least Load Routing (LLR) concept and the approach is to select the least load links for establishing connections. We propose a modiied version, called Ag-gregated Least Load Multicast Routing (ALLMR), wh...

This work describes the identification of designs that benefit from a Dynamic Circuit Specialization (DCS) implementation on FPGAs. In DCS, the circuit is specialized for slowly changing inputs, called parameters. For certain applications or cores, a DCS implementation is faster and smaller than the original implementation. DCS implementations can benefit from the possibility in modern FPGAs to...

A Novel circuit configuration for realizing multi-output four-terminal floating nullor in biopolar monolithic integrated circuit form is described. The circuit is simple and based on the use of an improved translinear cell type circuit, which provide wide bandwidth and dynamic range. The characteristics of this circuit are confirmed by HSPICE simulation results. The performance of the FTFN-base...

The functions of neural system, such as learning, recognition and memory, are the emergences from the elementary dynamic mechanisms. To discuss how the dynamic mechanisms in the neurons and synapses work in the function of recognition, a dynamic neural circuit is designed. In the neural circuit, the information is expressed as the inter-spike intervals of the spike trains. The neural circuit wi...

In this paper we present two techniques for improving min-area retiming that combine the actual register minimization with combinational optimization. First, we discuss an on-the-fly retiming approach based on a sequential AND/INVERTER/REGISTER graph. With this method the circuit structure is sequentially compacted using a combination of register “dragging” and AND vertex hashing. Second, we pr...