This paper presents a study of the relationship between Electrical Discharge Machining (EDM) parameters on the EDM efficiency factors using a full factorial design, based on pulse on-time, duty cycle and tool polarity parameters in EDM machining of AISI H13 tool steel. The results show that, in positive polarity, the plasma flushing efficiency and pulse efficiency increase according to the puls...

This concise presents a Modified Successive Approximation Register (MSAR)-based duty cycle corrector (DCC), which achieves low jitter, fast lock time with an accurate 50% duty cycle correction. This Modified SAR adopts a binary search method to condense lock time while maintaining tight synchronization between effort and production clocks. The projected DCC consists of a duty-cycle detector, a ...

In this paper, a generalized buck-boost Z-H converter based on switched inductors is proposed. This structure consists of a set of series connected switched-inductor cells. The voltage conversion ratio of the proposed structure is adjusted by changing the number of cells and the duty cycle. Like the conventional Z-H converter, the shoot-through switching state and the diode before LC network ar...

Economic lot size scheduling problem (ELSP) for a multi-product single machine system is a classical problem. This paper considers ELSP with budgetary constraint as an important aspect of such systems. In the real world situations the available funds for investment in inventory is limited. By adopting the common cycle time approach to ELSP, we obtain the optimal common cycle which minimizes the...

(ABSTRACT) In order to save energy consumption in idle states, low duty-cycled operation is widely used in Wireless Sensor Networks (WSNs), where each node periodically switches between sleeping mode and awake mode. Although efficient toward saving energy, duty-cycling causes many challenges , such as difficulty in neighbor discovery due to asynchronous wakeup/sleep scheduling, time-varying tra...

A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is presented in this paper. The proposed ADDCC can correct the duty-cycle error of the input clock to 50% duty-cycle. The acceptable duty-cycle range and frequency range of input clock is from 20% to 80% and from 250MHz to 1GHz, respectively. The proposed ADDCC is implemented on a standard performance 65 nm ...

Most of sensor MAC protocols have a fixed duty cycle, which performs poorly under the dynamic traffic condition observed in eventdriven sensor applications such as surveillance, fire detection, and objecttracking system. This paper proposes a traffic-aware MAC protocol which dynamically adjusts the duty cycle adapting to the traffic load. Our adaptive scheme operates on a tree topology, and nod...

Work and heat production of white myotomal muscle fibres from dogfish were measured during sinusoidal movement (0.71-5.0 Hz) at 12 C. Stimulus phase (stimulus timing relative to movement) and duty cycle (stimulus duration as a fraction of movement cycle duration) were varied to determine the parameters optimal for power output and for efficiency (work/total energy output). Movements of 0.067 an...

For maximum conservation of energy in sensor networks, one of the most effective approaches