This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author’s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: me...

A motion-cueing algorithm is a motion simulation system that makes the pilot feel flight by calculating attitude of platform. This paper presents design kinematics model and two algorithms for multi-axis Firstly, relationship between each axis derived from theory platform transformation. Next, are designed providing with bodily sensations 6-DoF By using hardware-in-the-loop (HIL) approach simul...

To meet increasing performance requirements of DSP applications, application specific processor designs, e.g. function unit (FU) duplication and register file (RF) distribution, are widely used in the design of DSP processors. In this paper, an application specific approach is proposed for the design of interconnection network in such DSP processors. By extracting the scheduling information of ...

We have developed a new-generation, general-purpose digital signal processor (DSP) core with low power dissipation for use in third-generation (3G) mobile terminals. The DSP core employs a 4-way VLIW (very long instruction word) approach, as well as a dual-multiply-accumulate (dual-MAC) architecture with good orthogonality. It is able to perform both video and speech codec for 3G wireless commu...

A new model for dynamic current analysis and simulation is presented for power and energy analysis of a complex VLIW DSP processor core, targeting secure wireless communications. Unlike other research, an instruction level RC based model, whose input parameters can be extracted from the DSP core's assembly level program, is introduced for power simulation. Experimental results utilizing several...

In this paper we present Pepsy, a novel prototyping environment for multiDSP systems, with the primary goal to support the design and implementation of parallel digital signal processing (DSP) applications subject to various design constraints. Given a specification of the prototyping problem in the form of an application model, a hardware model and mapping constraints, Pepsy automatically maps...

This paper describes an algorithm for name (surnames and personal names) announcement in American English implemented on DSP Group’s SmartCores (registered trademark) digital signal processor (dsp) core. The name announcement module is targeted for low cost applications therefor the amount of memory that can be allocated for dictionaries, program code, and runtime parameters is limited. The req...

Digital Signal Processing functions are widely used in real time high speed applications. Those functions are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtrac...

Digital image compression is a very popular topic in the field of multimedia processing. The major focus of work is to develop different compression schemes/algorithms to provide good visual quality fewer bit to represent an image in digital format. This paper work describes software and hardware implementation of Embedded Zerotree Wavelet (EZW) image Coder-Decoder (CODEC).The EZW image CODEC i...

In this paper we have proposed the design of a DSP microcontroller where the processor load is significantly reduced by relegating the math-intensive DSP algorithm to dedicated transform computing modules. It is shown that the use of such transform modules will facilitate scalability, reusability and flexibility for implementation of wide varieties of DSP functionalities. Moreover, it would be ...