Sub/near-threshold static random-access memory (SRAM) design is crucial for addressing the bottleneck in power-constrained applications. However, high integration density and reliability under process variations demand an accurate estimation of extremely small failure probabilities. To capture such a “rare event” circuits, time storage overhead conventional simulations based on Monte Carlo (MC)...

The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm are simulated. Simulations show that with a fixed channel length, when the gate length is increased, the output drain current characteristics slope is increas...

As scaling down MOSFET devices degrade device performance in term of leakage current and short channel effects. To overcome the problem a newer device Silicon-on-Insulator (SOI) MOSFET has been introduced. The Fully Depleted (FD) SOI MOSFETs also suffer from short channel effects (SCE) in the sub 65 nm regime due to reduction in threshold voltage. Several investigations are going to reduce the ...

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities ( gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is obs...

Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60mV/decade subthreshold swing and very small OFF current (IOFF), its practical application is questionable due to low ON current (ION) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60mV/decade subthreshold swi...

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction cha...

The Triple gate FinFET architecture has emerged as a viable contender for the ultimate scalability of CMOS devices. FinFET structure offers better control over device leakage currents than the conventional bulk MOSFET structure. In this paper, we present the 6 transistor (6T) SRAM cell implementation using the 22 nm gate length FinFET devices modeled using a 3-D device simulator. The performanc...

The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power application...

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper r...