Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe shortchannel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper...

The physical dimensions of bulk MOSFETs have been aggressively scaled down and these conventional devices will soon be experiencing limited improvements due to the scaling down. In order to continue performance improvements, new device architectures are needed. As the scaling of MOSFET into sub-100nm regime, SOI and DG-MOSFET are expect to replace traditional bulk MOSFET. These novel MOSFET dev...

As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. In this perspective two-dimensional transition metal dichalcogenides, such as MoS2 and WSe2, have recently attracted considerable interest thanks to their electrical ...

Analysis of the electrostatic characteristics and the gate capacitance of typical nanostructured carbon nanotube field effect transistors (CNTFETs) were performed numerically. A previously developed parallelized electrostatic Poisson’s equation solver (PPES) is employed, coupled with a parallel adaptive mesh refinement (PAMR) to improve the numerical accuracy near the region where variation of ...

The first realization of a biomolecular OR gate function with double-sigmoid response (sigmoid in both inputs) is reported. Two chemical inputs activate the enzymatic gate processes, resulting in the output signal: chromogen oxidation, which occurs when either one of the inputs or both are present (corresponding to the OR binary function), and can be optically detected. High-quality gate functi...

The Double Gate FinFET has been designed for 90nm as an alternative solution to bulk devices. The FinFET with independent gate (IDG) structure is designed to control Vth. When the Vth is controlled the leakage current can be decreased by improving its current driving capability. The metal used for the front gate and back gate is TiN. Here the device performance is compared using nitride spacer ...

Gate tunneling current in fully depleted, double-gate (DG) silicon-on-insultor (SOI) MOSFETs is characterized based on quantummechanical principles. The gate tunneling current for symmetrical DG SOI with ground-plane ( =1.5 nm and =5 nm) is shown to be higher relative to single-gate (bulk) MOS structure. The tunneling is enhanced as the silicon layer becomes thinner since the thinner silicon la...

We propose a set of universal gate operations for the singlet-triplet qubit realized by two-electron spins in a double quantum dot, in the presence of a fixed inhomogeneous magnetic field. All gate operations are achieved by switching the potential offset between the two dots with an electrical bias, and do not require time-dependent control of the tunnel coupling between the dots. We analyze t...

Continued miniaturization of bulk silicon CMOS transistors is being limited by degrading short channel effects. Traditionally, higher channel doping, shallower source/drain junctions, and thinner gate dielectrics have been employed to improve gate control and enhance performance as the gate length is scaled down. However, these techniques are rapidly approaching material and process limits. Alt...