Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

This paper presents a novel quad-band power divider with equal power division ratio. The proposed power divider is realized using two cascaded sections of dual-band transformers based on coupled microstrip lines. Limitations of using dual-band quarterwavelength transformers based on coupled lines are studied through parametric analysis to obtain useful design guidelines related to available fab...

The behavior of two frequency divider circuits using negative differential resistance (NDR) circuit is studied. This NDR circuit is made of three resistors (R) and two bipolar-junction-transistor (BJT) devices. It can show the NDR characteristic in its current-voltage curve by suitably designing the resistances. We discuss a dynamic frequency divider, which is made of a R-BJT-NDR circuit, an in...

A 1 V low voltage delta-sigma fractional-N frequency divider for multi-band (780/868/915 MHz and 2.4 GHz) WSN frequency synthesizers is presented. The frequency divider consists of a dual-modulus prescaler, a pulse-swallow counter and a delta-sigma modulator. The high-speed and low-voltage phase-switching dualmodulus prescaler is used in the frequency divider. Low threshold voltage transistors ...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

This paper proposes a divider structure that combines a novel self-timed ring structure and a carry-propagation-free division algorithm. The self-timed ring structure enables the divider to compute at a speed comparable to that of previously designed dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, we can achieve even better performance. We designed ...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

An unsigned 8-bit ÷ 4-bit delay-insensitive iterative divider is developed using the NULL Convention Logic paradigm. The divider is simulated using a 0.5μm CMOS process with static cells. The simulation of the initial design yielded an average cycle time of 75.92 ns with a transistor count of 4,721. A subsequent design increased throughput by 18%, while only increasing area by 2.7%.

The traceability chain to derive the capacitance unit from the quantum Hall resistance coaxial bridges. These bridges employ a inductive voltage divider to provide the voltage ratio needed. One such divider has recently been constructed calibrated at Inmetro. The design techniques responsible for the small ratio errors of the device are detailed

We realize and investigate a wavelength-flexible phase-coherent all-optical frequency-by-2 divider. Frequency division is obtained via self-phase locking in a degenerate continuous-wave (cw) optical parametric oscillator (OPO). The wavelength flexibility of the divider is based on the use of quasiphase matching (QPM) with perpendicular polarizations of the OPO output waves (type II). Mutual inj...