In this paper it is shown that zero-input overflow limit cycles can be suppressed in a class of lossless digital integrator (LDI) all-pass filters, namely, that introduced in [1]. This holds for any filter order, provided that saturation overflow characteristics are used at the input of each delay and for certain restrictions for the multiplier values. The results are shown to apply also to los...

We propose and experimentally prove a novel design for implementing photonic temporal integrators simultaneously offering a high processing bandwidth and a long operation time window, namely a large time-bandwidth product. The proposed scheme is based on concatenating in series a time-limited ultrafast photonic temporal integrator, e.g. implemented using a fiber Bragg grating (FBG), with a disc...

Adaptive noise cancellation (ANC) technique can removes thermal and shaped wideband quantization noise from the output of sigma-delta modulator and improves SNR and SFDR ratios. ANC filter more than desired signal passes harmonics of input signal caused by analog element such as operational amplifier of the integrator without any suppression and this issue causes less increment in SNR and SFDR ...

Electrocardiogram (ECG) is one of the most important parameters for heart activity monitoring. The main objective of digital signal processing of ECG signal is to deliver accurate, fast and reliable estimation of clinically important parameters such as the duration of the QRS complex, the R-R interval, the occurrence, amplitude and duration of the P, R, and T waves. In this paper, I have measur...

Presented in this paper is a low power, area efficient reconfigurable analog-to-digital (ADC) converter, utilising a charge-summation technique with a switched-capacitor implementation. Using a non-inverting switched-capacitor integrator a staircase ramp is produced using switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation techn...

Implementation of wireless wideband transmitters using ∆Σ DACs requires very high speed modulators. Digital MASH ∆Σ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ∆Σ modulators. The bottlenecks for a high-speed operation are id...

In this paper, the designing of decimation filter for sigma-delta (∑-∆) ADC having different oversampling ratio (OSR) is described. The decimation filter perform the operation of down sampling of a high frequency, low resolution signal to Nyquist rate, high resolution digital output. The design of a decimation filter is projected that employs two stagesCascaded Integrator Comb (CIC) filters and...

This paper presents a novel diversity-controlled (DC) genetic algorithm (GA) for the optimization of digital Intermediate Frequency (IF) filters over the (finiteprecision) canonical signed-digit (CSD) multiplier coefficient space. This optimization exploits the bilinear-losslessdiscrete-integrator (bilinear-LDI) lattice digital filter design approach for the realization of the required infinite...

A digital output is more desirable than an analog output in noisy environments (e.g., automotive, washing machines) and remote sensing applications (e.g., building controls, industrial applications) because a digital signal inherently has better noise immunity compared to analog signals. Additional applications requiring a sensor with a digital output include microcontroller-based systems that ...

This paper is concerned with the discretization of the fractional-order differentiator and integrator, which is the foundation of the digital realization of fractional order controller. Firstly, the parameterized Al-Alaoui transform is presented as a general generating function with one variable parameter, which can be adjusted to obtain the commonly used generating functions (e.g. Euler operat...