In this paper, we address the following problem: given a synchronous digital circuit, is it possible to construct a new circuit computing the same function as the original one but using a minimal number of registers? The construction of such a circuit can be done in polynomial time and is based on a result of Orlin for one periodic bi-infinite graphs showing that the cardinality maximum flow is...

ETRI Journal, Volume 29, Number 1, February 2007 A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow lowvoltage circuit operation. A simple 1-bit first-order deltasigma modulator is used to produce an output digital bitstre...

This work is concerned about the design process of high performance integrated circuits in presence of noise produced by large high-speed digital circuits in the same die. In a more specific context, it deals with the early estimation of the substrate and simultaneous switching noise produced by digital circuits, its propagation and, in minor extent, its impact in the noise sensitive radio freq...

We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Virtex-II Pro FPGA, the system provides an innovative single-chip solution for protecting digital content. In the system, a partial circuit must be downloaded from a server to the client terminal to play content. Content ...

Most of the digital circuits are categorized into the synchronous circuit which uses a clock signal to alter its internal state such that a digital signal is latched by a flip-flop in the timing specified by a clock signal. Therefore, even if a digital signal suffers from ”hazard” in between two consecutive raising edges of a clock signal, a correct signal is successfully latched if the signal ...