n ±1 are the most popular moduli in Residue Number Systems (RNS), a large variety of modulo 2 n ±1 adder designs have been proposed based on different number representations. However, in most of the cases, these encodings do not allow the implementation of a unified adder for all the moduli of the form 2 n-1, 2 n , and 2 n +1. In this paper, we address the modular addition issue by introducing ...

Full adders are important components in applications such as digital signal processing (DSP) architecture, and microprocessors. Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using adiabatic logic style (DTGAL), which are derived from static CMOS logic, without a large change. This paper also proposes a new design ...

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based ...

Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture beco...

In this paper, 1 bit full adder is built under a new hybrid logic (combination of PTL and CMOS logic) style, using 14 MOSFETs. Here we use 6transistor XOR-XNOR circuit to implement the full adder. This full adder offers full voltage swing at every nodes, higher density and high speed than the conventional CMOS design style. TSPICE is the simulator used for the simulation and bsim3v32 technology...

This paper describes the design of the 56-bit signifcand adder for the Advanced Micro Devices Am290.501 microprocessor. This is a 1 pm design rule CMOS realization of a high performance RISC microprocessor that implements IEEE Standard 754 floating point arithmetic. To achieve an add time of under 4 ns for the 56-bit significand and to avoid multistage pipelines which signijlcantly impair compi...

Arithmetic and Logic Unit (ALU), core unit of a processor, when used for scientific computations, will spend more time in multiplications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reducing delay in the multiplier reduces the overall computation time. Wallace multipliers perform in parallel, resulting in high speed. It uses...

Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is b...