Random device mismatch have a significant impact on the performance of analog circuits. This report discusses the design of a Delay Lock Loop (DLL) which is insensitive to process variation. The DLL is optimized for reduction in the variation of threshold voltage variations and is intended to be used in a clock and data recovery circuit with an input bit rate of 500 Mbps. The performance specif...

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occup...

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (~25ps – 800ps binning) and a dynamic range of 102.4μs has been implemented in a 0.25μm CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time...

Under 500ps Yong-Bin Kim Tom Chen Department of Electrical Engineering Colorado State University Abstract This paper presents a variable delay line DLL circuit implemented in a 0.8 m CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The...

AB!3TRACT CDMA systems require synchronization between the received sequence and the locally generated sequence. This is done by means of a Delay-Lock Loop (DLL). The differential equation of an incoherent secondorder DLL has been programmed. The Mean Time to Lose Lock (MTLL) of the DLL is a very important design parameter. We have obtained this parameter by computer simulation and we are able ...

GPS timing and navigation user solutions are based on pseudorange measurements made by correlating user receiver-generated replica signals with the signals broadcast by the GPS satellites. Any bias resulting from this correlation process within the user receiver tends to be common across all receiver channels when the signal characteristics are identical (code type, modulation type, and bandwid...

The influence of code synchronization errors on the performance of direct-sequence spread-spectrum (DS/SS) communication systems is investigated. Insight is gained in the degradation of some basic performance parameters due to the tracking bias of a noncoherent delay lock loop (DLL). The performance parameters investigated are the bit-error probability, throughput and delay. Numerical results s...

A 3-5 GHz UWB radar chip in 0.13 m CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter,...

Since very short pulse waves are transmitted, UWB systems have excellent accuracy in terms of distance measurement. In order to measure the distance between the terminals, the transmitted pulses have to be synchronized by a delay-lock-loop (DLL) in the receiver. In this paper the performance of the DLL is evaluated. Its performance depends the timing jitter between the local clocks of the termi...

In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. In this paper a novel surfing technique is proposed for differential wave-pipelined serial interconnects, which uses a 'Controllable inverter pair' for surfing. To evaluate the efficiency of this technique, a transceiver with transmitter, receiver, dela...